Re: [PATCH 5/8] drm/i915/skl: Implement enable/disable for Display C6 state.

[Imre Deak <imre.deak@intel.com>]

On Wed, 2015-04-01 at 16:22 +0530, Animesh Manna wrote:
> From: "A.Sunil Kamath" <sunil.kamath@intel.com>
> 
> This patch just implements the basic enable and disable
> functions of DC6 state which is needed for SKL platform.
> 
> Its important to load SKL CSR program before calling enable.
> 
> DC6 is a deeper power saving state where hardware dynamically
> disables power well 0 and saves the associated registers.
> DC6 can be entered when software allows it, the conditions
> for DC5 are met, and the PCU allows DC6.
> DC6 cannot be used if the backlight is being driven from the
> display utility pin.
> 
> Its better to configure display engine to have power well 2
> disabled before getting into DC6 enable function. Hence rpm
> framework will ensure to check status of power well 2 and DC5
> before calling skl_enable_dc6.
> 
> v2: Replace HAS_ with IS_ check as per Daniel's review comments
> 
> v3: Cleared the bits dc5/dc6 enable of DC_STATE_EN register
> before setting them as per Satheesh's review comments.
> 
> v4: No need to call gen9_disable_dc5 inside enable sequence of
> DC6, as its already take care above.
> 
> v5: call POSTING_READ for every write to a register to ensure that
> its written immediately.
> Call intel_prepare_ddi during DC6 exit as it's required on low-power exit.
> 
> v6: Protect DC6-enabling-disabling functionality with locks to synchronize
> with CSR-loading code.
> 
> v7: Remove grabbing CSR-related mutex in skl_enable/disable_dc6 functions as
>     deferred DC5-enabling functionality is now removed.
> 
> v8: Remove 'Disabling DC5' from the debug comment during DC6 enabling as when
>     DC6 is allowed, DC5 is not programmed at all.
> 
> v9:
> 1] Rebase to latest.
> 2] Move all DC6-related functions from intel_display.c to intel_runtime_pm.c.
> 
> v10: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
> 
> Issue: VIZ-2819
> Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 35 +++++++++++++++++++++++++++++++++
>  1 file changed, 35 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index f62d42b..dae65e0 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -407,6 +407,41 @@ static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
>  	POSTING_READ(DC_STATE_EN);
>  }
>  
> +static void skl_enable_dc6(struct drm_i915_private *dev_priv)
> +{
> +	struct drm_device *dev = dev_priv->dev;
> +	uint32_t val;
> +
> +	WARN_ON(!IS_SKYLAKE(dev));
> +
> +	DRM_DEBUG_KMS("Enabling DC6\n");
> +
> +	gen9_set_dc_state_debugmask_memory_up(dev_priv);
> +
> +	val = I915_READ(DC_STATE_EN);
> +	val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
> +	val |= DC_STATE_EN_UPTO_DC6;
> +	I915_WRITE(DC_STATE_EN, val);
> +	POSTING_READ(DC_STATE_EN);
> +}
> +
> +static void skl_disable_dc6(struct drm_i915_private *dev_priv)
> +{
> +	struct drm_device *dev = dev_priv->dev;
> +	uint32_t val;
> +
> +	WARN_ON(!IS_SKYLAKE(dev));
> +
> +	DRM_DEBUG_KMS("Disabling DC6\n");
> +
> +	val = I915_READ(DC_STATE_EN);
> +	val &= ~DC_STATE_EN_UPTO_DC6;
> +	I915_WRITE(DC_STATE_EN, val);
> +	POSTING_READ(DC_STATE_EN);
> +
> +	intel_prepare_ddi(dev);
> +}
> +
>  static void skl_set_power_well(struct drm_i915_private *dev_priv,
>  			struct i915_power_well *power_well, bool enable)
>  {


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