Re: [PATCH 05/19] drm/i915: ILK cdclk seems to be 450MHz

Damien Lespiau
2015-03-31T13:13:28Z

On Tue, Mar 31, 2015 at 02:11:54PM +0300, Mika Kahola wrote:
> Based on the BIOS DP A AUX 2x clock divider the cdclk frequency
> on ILK is 450Mhz. At least that holds on my ILK and it matches
> how we program the divider.
>
> Supposedly cdclk is 400MHz on SNB and IVB, again based on the AUX 2x
> clock divider. Note that I don't have a SNB or IVB machine with
> eDP so I couldn't verify what the BIOS used, so this notion is
> purely based on our current code,
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

> ---
> drivers/gpu/drm/i915/intel_display.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index bebbfd2..5df9c47 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5886,6 +5886,11 @@ static int valleyview_get_display_clock_speed(struct drm_device *dev)
> return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
> }
>
> +static int ilk_get_display_clock_speed(struct drm_device *dev)
> +{
> + return 450000;
> +}
> +
> static int i945_get_display_clock_speed(struct drm_device *dev)
> {
> return 400000;
> @@ -13685,6 +13690,9 @@ static void intel_init_display(struct drm_device *dev)
> if (IS_VALLEYVIEW(dev))
> dev_priv->display.get_display_clock_speed =
> valleyview_get_display_clock_speed;
> + else if (IS_GEN5(dev))
> + dev_priv->display.get_display_clock_speed =
> + ilk_get_display_clock_speed;
> else if (IS_GM45(dev))
> dev_priv->display.get_display_clock_speed =
> gm45_get_display_clock_speed;
> --
> 1.9.1
>
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