From: deepak.s@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v3] drm/i915: Setup static bias for GPU
Date: Wed, 29 Apr 2015 08:36:24 +0530 [thread overview]
Message-ID: <1430276784-7228-1-git-send-email-deepak.s@linux.intel.com> (raw)
In-Reply-To: <1430275883-3366-1-git-send-email-deepak.s@linux.intel.com>
From: Deepak S <deepak.s@linux.intel.com>
Based on the spec, Setting up static BIAS for GPU to improve the
rps performace.
v2: rename reg defn to match spec. (Ville)
v3: Updated bias setting for chv (Deepak)
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++++++
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 36805b6..048987e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -670,6 +670,12 @@ enum skl_disp_power_wells {
#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
+#define VLV_TURBO_SOC_OVERRIDE 0x04
+#define VLV_OVERRIDE_EN 1
+#define VLV_SOC_TDP_EN (1 << 1)
+#define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
+#define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
+
#define VLV_CZ_CLOCK_TO_MILLI_SEC 100000
/* vlv2 north clock has */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 78c89ff..3689d0e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5065,6 +5065,12 @@ static void cherryview_enable_rps(struct drm_device *dev)
GEN6_RP_UP_BUSY_AVG |
GEN6_RP_DOWN_IDLE_AVG);
+ /* Setting Fixed Bias */
+ val = VLV_OVERRIDE_EN |
+ VLV_SOC_TDP_EN |
+ CHV_BIAS_CPU_50_SOC_50;
+ vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
+
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
/* RPS code assumes GPLL is used */
@@ -5149,6 +5155,12 @@ static void valleyview_enable_rps(struct drm_device *dev)
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
+ /* Setting Fixed Bias */
+ val = VLV_OVERRIDE_EN |
+ VLV_SOC_TDP_EN |
+ VLV_BIAS_CPU_125_SOC_875;
+ vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
+
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
/* RPS code assumes GPLL is used */
--
1.9.1
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next prev parent reply other threads:[~2015-04-29 3:09 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-28 9:53 [PATCH v3 0/5] CHV PM fix & Improvements deepak.s
2015-03-28 9:53 ` [PATCH v3 1/5] drm/i915/chv: Remove Wait for a previous gfx force-off deepak.s
2015-03-30 10:07 ` Ville Syrjälä
2015-03-30 14:32 ` Deepak S
2015-03-30 15:41 ` Daniel Vetter
2015-03-28 9:53 ` [PATCH v3 2/5] drm/i915: Re-adjusting rc6 promotional timer for chv deepak.s
2015-04-16 15:26 ` Daniel Vetter
2015-03-28 9:53 ` [PATCH v3 3/5] drm/i915/chv: Set min freq to efficient frequency on chv deepak.s
2015-04-29 2:53 ` [PATCH v4] " deepak.s
2015-04-29 15:31 ` Ville Syrjälä
2015-04-29 19:53 ` Ville Syrjälä
2015-04-30 10:12 ` Deepak S
2015-04-30 11:19 ` Ville Syrjälä
2015-04-30 14:05 ` Ville Syrjälä
2015-05-02 7:26 ` Deepak S
2015-04-30 2:42 ` shuang.he
2015-05-04 8:04 ` Daniel Vetter
2015-03-28 9:53 ` [PATCH v3 4/5] drm/i915/chv: Remove unused rps min function deepak.s
2015-03-28 9:53 ` [PATCH v3 5/5] drm/i915: Setup static bias for GPU deepak.s
2015-03-28 12:20 ` shuang.he
2015-03-30 9:56 ` Ville Syrjälä
2015-04-29 2:51 ` [PATCH v2] " deepak.s
2015-04-29 3:06 ` deepak.s [this message]
2015-04-29 9:29 ` [PATCH v3] " Ville Syrjälä
2015-05-04 5:28 ` Deepak S
2015-05-04 8:12 ` Daniel Vetter
2015-05-04 15:28 ` Ville Syrjälä
2015-05-05 7:42 ` Deepak S
2015-05-06 9:02 ` Daniel Vetter
2015-05-08 15:06 ` Deepak S
2015-04-30 6:56 ` shuang.he
2015-04-29 23:00 ` [PATCH v2] " shuang.he
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