From: Imre Deak <imre.deak@intel.com>
To: Nick Hoath <nicholas.hoath@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i195/bxt: Add A1 stepping for Broxton
Date: Wed, 29 Apr 2015 17:35:14 +0300 [thread overview]
Message-ID: <1430318114.1811.41.camel@intel.com> (raw)
In-Reply-To: <1426843779-7139-1-git-send-email-nicholas.hoath@intel.com>
On pe, 2015-03-20 at 09:29 +0000, Nick Hoath wrote:
> This stepping isn't listed separately in the specs, so needs confirmation.
>
> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index eec271a..68fb41a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2329,6 +2329,7 @@ struct drm_i915_cmd_table {
> #define SKL_REVID_E0 (0x4)
>
> #define BXT_REVID_A0 (0x0)
> +#define BXT_REVID_A1 (0x1)
The above mapping is for the SOC RevID, but I think for all our purposes
(WAs) we should check the GT/Display RevID. The A1 GT/Display RevID
doesn't seem to exist, only A0 is defined with all of 0,1,2 RevIDs
mapping to A0.
> #define BXT_REVID_B0 (0x3)
> #define BXT_REVID_C0 (0x6)
>
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next prev parent reply other threads:[~2015-04-29 14:35 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-20 9:29 [PATCH] drm/i195/bxt: Add A1 stepping for Broxton Nick Hoath
2015-03-20 17:14 ` shuang.he
2015-03-20 19:17 ` Jesse Barnes
2015-03-21 1:20 ` He, Shuang
2015-04-29 14:35 ` Imre Deak [this message]
2015-05-05 14:20 ` Nick Hoath
2015-05-05 16:18 ` Imre Deak
2015-05-06 16:00 ` Nick Hoath
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