[PATCH] drm/i195/bxt: Add A1 stepping for Broxton

[PATCH] drm/i195/bxt: Add A1 stepping for Broxton

[Nick Hoath]

This stepping isn't listed separately in the specs, so needs confirmation.

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index eec271a..68fb41a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2329,6 +2329,7 @@ struct drm_i915_cmd_table {
 #define SKL_REVID_E0		(0x4)
 
 #define BXT_REVID_A0		(0x0)
+#define BXT_REVID_A1		(0x1)
 #define BXT_REVID_B0		(0x3)
 #define BXT_REVID_C0		(0x6)
 
-- 
2.1.1

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Re: [PATCH] drm/i195/bxt: Add A1 stepping for Broxton

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6016
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -2              274/274              272/274
ILK                                  303/303              303/303
SNB                                  303/303              303/303
IVB                 -2              342/342              340/342
BYT                                  287/287              287/287
HSW                                  362/362              362/362
BDW                                  308/308              308/308
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*PNV  igt_gem_userptr_blits_minor-sync-interruptible      PASS(2)      DMESG_WARN(1)PASS(1)
*PNV  igt_gen3_render_linear_blits      PASS(3)      CRASH(1)PASS(1)
 IVB  igt_gem_pwrite_pread_snooped-copy-performance      DMESG_WARN(1)PASS(3)      DMESG_WARN(1)PASS(1)
*IVB  igt_gem_storedw_batches_loop_secure-dispatch      PASS(3)      DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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Re: [PATCH] drm/i195/bxt: Add A1 stepping for Broxton

[Jesse Barnes]

On 03/20/2015 10:14 AM, shuang.he@intel.com wrote:
> Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
> Task id: 6016
> -------------------------------------Summary-------------------------------------
> Platform          Delta          drm-intel-nightly          Series Applied
> PNV                 -2              274/274              272/274
> ILK                                  303/303              303/303
> SNB                                  303/303              303/303
> IVB                 -2              342/342              340/342
> BYT                                  287/287              287/287
> HSW                                  362/362              362/362
> BDW                                  308/308              308/308
> -------------------------------------Detailed-------------------------------------
> Platform  Test                                drm-intel-nightly          Series Applied
> *PNV  igt_gem_userptr_blits_minor-sync-interruptible      PASS(2)      DMESG_WARN(1)PASS(1)
> *PNV  igt_gen3_render_linear_blits      PASS(3)      CRASH(1)PASS(1)
>  IVB  igt_gem_pwrite_pread_snooped-copy-performance      DMESG_WARN(1)PASS(3)      DMESG_WARN(1)PASS(1)
> *IVB  igt_gem_storedw_batches_loop_secure-dispatch      PASS(3)      DMESG_WARN(1)PASS(1)
> Note: You need to pay more attention to line start with '*'

I wonder what these warnings actually are... I've been seeing the
userptr_blits tests on PNV trigger warnings in a lot of PRTS results
lately, and it must be intermittent since this patch would have no
effect on PNV.

Shuang, when do you think you'll be able to attach the dmesg snippets
from failures like these to the  msgs?  Would make things easier to
triage at least.

And do we have a bug open?  I don't see this particular issue listed in
the igt failures at bugs.fdo, but it could be a dupe with some other
warning there.

Thanks,
Jesse

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Re: [PATCH] drm/i195/bxt: Add A1 stepping for Broxton

[He, Shuang]

> -----Original Message-----
> From: Jesse Barnes [mailto:jbarnes@virtuousgeek.org]
> Sent: Saturday, March 21, 2015 3:17 AM
> To: He, Shuang; Gao, Ethan; intel-gfx@lists.freedesktop.org; Hoath, Nicholas
> Subject: Re: [Intel-gfx] [PATCH] drm/i195/bxt: Add A1 stepping for Broxton
> 
> On 03/20/2015 10:14 AM, shuang.he@intel.com wrote:
> > Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
> shuang.he@intel.com)
> > Task id: 6016
> > -------------------------------------Summary-------------------------------------
> > Platform          Delta          drm-intel-nightly          Series Applied
> > PNV                 -2              274/274              272/274
> > ILK                                  303/303              303/303
> > SNB                                  303/303              303/303
> > IVB                 -2              342/342              340/342
> > BYT                                  287/287              287/287
> > HSW                                  362/362              362/362
> > BDW                                  308/308              308/308
> > -------------------------------------Detailed-------------------------------------
> > Platform  Test                                drm-intel-nightly          Series Applied
> > *PNV  igt_gem_userptr_blits_minor-sync-interruptible      PASS(2)
> DMESG_WARN(1)PASS(1)
> > *PNV  igt_gen3_render_linear_blits      PASS(3)      CRASH(1)PASS(1)
> >  IVB  igt_gem_pwrite_pread_snooped-copy-performance
> DMESG_WARN(1)PASS(3)      DMESG_WARN(1)PASS(1)
> > *IVB  igt_gem_storedw_batches_loop_secure-dispatch      PASS(3)
> DMESG_WARN(1)PASS(1)
> > Note: You need to pay more attention to line start with '*'
> 
> I wonder what these warnings actually are... I've been seeing the
> userptr_blits tests on PNV trigger warnings in a lot of PRTS results
> lately, and it must be intermittent since this patch would have no
> effect on PNV.
> 
> Shuang, when do you think you'll be able to attach the dmesg snippets
> from failures like these to the  msgs?  Would make things easier to
> triage at least.
[He, Shuang] yeah, it makes sense, we will see how we can improve this

> 
> And do we have a bug open?  I don't see this particular issue listed in
> the igt failures at bugs.fdo, but it could be a dupe with some other
> warning there.
[He, Shuang] I'll forward this to QA guys working on kernel validation, see if they already have this tracked

Thanks
	--Shuang
> 
> Thanks,
> Jesse

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Re: [PATCH] drm/i195/bxt: Add A1 stepping for Broxton

[Imre Deak]

On pe, 2015-03-20 at 09:29 +0000, Nick Hoath wrote:
> This stepping isn't listed separately in the specs, so needs confirmation.
> 
> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index eec271a..68fb41a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2329,6 +2329,7 @@ struct drm_i915_cmd_table {
>  #define SKL_REVID_E0		(0x4)
>  
>  #define BXT_REVID_A0		(0x0)
> +#define BXT_REVID_A1		(0x1)

The above mapping is for the SOC RevID, but I think for all our purposes
(WAs) we should check the GT/Display RevID. The A1 GT/Display RevID
doesn't seem to exist, only A0 is defined with all of 0,1,2 RevIDs
mapping to A0.

>  #define BXT_REVID_B0		(0x3)
>  #define BXT_REVID_C0		(0x6)
>  


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Re: [PATCH] drm/i195/bxt: Add A1 stepping for Broxton

[Nick Hoath]

On 29/04/2015 15:35, Deak, Imre wrote:
> On pe, 2015-03-20 at 09:29 +0000, Nick Hoath wrote:
>> This stepping isn't listed separately in the specs, so needs confirmation.
>>
>> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_drv.h | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index eec271a..68fb41a 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2329,6 +2329,7 @@ struct drm_i915_cmd_table {
>>   #define SKL_REVID_E0		(0x4)
>>
>>   #define BXT_REVID_A0		(0x0)
>> +#define BXT_REVID_A1		(0x1)
>
> The above mapping is for the SOC RevID, but I think for all our purposes
> (WAs) we should check the GT/Display RevID. The A1 GT/Display RevID
> doesn't seem to exist, only A0 is defined with all of 0,1,2 RevIDs
> mapping to A0.

We use the GT Device2 Revision ID for these comparisons, which does 
change on each SoC revision. This may map to A0 GT stepping for all the 
Ax SoCs, according to the specs. However, as this is a naming convention 
that doesn't affect the code, I suggest we stick to what I have in this 
patch even if it doesn't 100% reflect what's in the specs.

>
>>   #define BXT_REVID_B0		(0x3)
>>   #define BXT_REVID_C0		(0x6)
>>
>
>

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Re: [PATCH] drm/i195/bxt: Add A1 stepping for Broxton

[Imre Deak]

On ti, 2015-05-05 at 15:20 +0100, Nick Hoath wrote:
> On 29/04/2015 15:35, Deak, Imre wrote:
> > On pe, 2015-03-20 at 09:29 +0000, Nick Hoath wrote:
> >> This stepping isn't listed separately in the specs, so needs confirmation.
> >>
> >> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/i915_drv.h | 1 +
> >>   1 file changed, 1 insertion(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> >> index eec271a..68fb41a 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -2329,6 +2329,7 @@ struct drm_i915_cmd_table {
> >>   #define SKL_REVID_E0		(0x4)
> >>
> >>   #define BXT_REVID_A0		(0x0)
> >> +#define BXT_REVID_A1		(0x1)
> >
> > The above mapping is for the SOC RevID, but I think for all our purposes
> > (WAs) we should check the GT/Display RevID. The A1 GT/Display RevID
> > doesn't seem to exist, only A0 is defined with all of 0,1,2 RevIDs
> > mapping to A0.
> 
> We use the GT Device2 Revision ID for these comparisons, which does 
> change on each SoC revision. This may map to A0 GT stepping for all the 
> Ax SoCs, according to the specs. However, as this is a naming convention 
> that doesn't affect the code, I suggest we stick to what I have in this 
> patch even if it doesn't 100% reflect what's in the specs.

Not sure about this, as I understand all the workarounds are marked with
the GT stepping not the SOC stepping, even though the latter is more
fine-grained. Is there any workarounds for A1? If not I'd suggest adding
this macro only when we need it.

--Imre

> >>   #define BXT_REVID_B0		(0x3)
> >>   #define BXT_REVID_C0		(0x6)
> >>
> >
> >
> 


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Re: [PATCH] drm/i195/bxt: Add A1 stepping for Broxton

[Nick Hoath]

On 05/05/2015 17:18, Deak, Imre wrote:
> On ti, 2015-05-05 at 15:20 +0100, Nick Hoath wrote:
>> On 29/04/2015 15:35, Deak, Imre wrote:
>>> On pe, 2015-03-20 at 09:29 +0000, Nick Hoath wrote:
>>>> This stepping isn't listed separately in the specs, so needs confirmation.
>>>>
>>>> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/i915/i915_drv.h | 1 +
>>>>    1 file changed, 1 insertion(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>>> index eec271a..68fb41a 100644
>>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>>> @@ -2329,6 +2329,7 @@ struct drm_i915_cmd_table {
>>>>    #define SKL_REVID_E0		(0x4)
>>>>
>>>>    #define BXT_REVID_A0		(0x0)
>>>> +#define BXT_REVID_A1		(0x1)
>>>
>>> The above mapping is for the SOC RevID, but I think for all our purposes
>>> (WAs) we should check the GT/Display RevID. The A1 GT/Display RevID
>>> doesn't seem to exist, only A0 is defined with all of 0,1,2 RevIDs
>>> mapping to A0.
>>
>> We use the GT Device2 Revision ID for these comparisons, which does
>> change on each SoC revision. This may map to A0 GT stepping for all the
>> Ax SoCs, according to the specs. However, as this is a naming convention
>> that doesn't affect the code, I suggest we stick to what I have in this
>> patch even if it doesn't 100% reflect what's in the specs.
>
> Not sure about this, as I understand all the workarounds are marked with
> the GT stepping not the SOC stepping, even though the latter is more
> fine-grained. Is there any workarounds for A1? If not I'd suggest adding
> this macro only when we need it.


Agreed, consider this patch currently N/A.

>
> --Imre
>
>>>>    #define BXT_REVID_B0		(0x3)
>>>>    #define BXT_REVID_C0		(0x6)
>>>>
>>>
>>>
>>
>
>

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