* [PATCH-V4 1/2] drm/i915/audio: add codec wakeup override enabled/disable callback
@ 2015-05-05 1:05 han.lu
2015-05-05 1:05 ` [PATCH-V4 2/2] ALSA:hda - reset display codec when power on han.lu
0 siblings, 1 reply; 3+ messages in thread
From: han.lu @ 2015-05-05 1:05 UTC (permalink / raw)
To: daniel.vetter, tiwai, jani.nikula, libin.yang, mengdong.lin,
intel-gfx
Cc: Lu, Han
From: "Lu, Han" <han.lu@intel.com>
Add support for enabling codec wakeup override signal to allow
re-enumeration of the controller on SKL after resume from low power state.
In SKL, HDMI/DP codec and PCH HD Audio Controller are in different power
wells, so it's necessary to reset display audio codecs when power well on,
otherwise display audio codecs will disappear when resume from low power
state.
Reset steps when power on:
enable codec wakeup -> azx_init_chip() -> disable codec wakeup
v3 by Jani: Simplify to only support toggling the appropriate chicken bit.
v4 by Han: add explanation and specify the hw swquence.
Signed-off-by: Lu, Han <han.lu@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 36805b6..435c372 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6881,6 +6881,9 @@ enum skl_disp_power_wells {
#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
+#define HSW_AUD_CHICKENBIT 0x65f10
+#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
+
/* HSW Power Wells */
#define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */
#define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index f72e93a..ceb2328 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -474,6 +474,32 @@ static void i915_audio_component_put_power(struct device *dev)
intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
}
+static void i915_audio_component_codec_wake_override(struct device *dev,
+ bool enable)
+{
+ struct drm_i915_private *dev_priv = dev_to_i915(dev);
+ u32 tmp;
+
+ if (!IS_SKYLAKE(dev_priv))
+ return;
+
+ /*
+ * Enable/disable generating the codec wake signal, overriding the
+ * internal logic to generate the codec wake to controller.
+ */
+ tmp = I915_READ(HSW_AUD_CHICKENBIT);
+ tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
+ I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
+ usleep_range(1000, 1500);
+
+ if (enable) {
+ tmp = I915_READ(HSW_AUD_CHICKENBIT);
+ tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
+ I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
+ usleep_range(1000, 1500);
+ }
+}
+
/* Get CDCLK in kHz */
static int i915_audio_component_get_cdclk_freq(struct device *dev)
{
@@ -495,6 +521,7 @@ static const struct i915_audio_component_ops i915_audio_component_ops = {
.owner = THIS_MODULE,
.get_power = i915_audio_component_get_power,
.put_power = i915_audio_component_put_power,
+ .codec_wake_override = i915_audio_component_codec_wake_override,
.get_cdclk_freq = i915_audio_component_get_cdclk_freq,
};
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index 3e2f22e..c9a8b64 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -31,6 +31,7 @@ struct i915_audio_component {
struct module *owner;
void (*get_power)(struct device *);
void (*put_power)(struct device *);
+ void (*codec_wake_override)(struct device *, bool enable);
int (*get_cdclk_freq)(struct device *);
} *ops;
};
--
1.9.1
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^ permalink raw reply related [flat|nested] 3+ messages in thread* [PATCH-V4 2/2] ALSA:hda - reset display codec when power on 2015-05-05 1:05 [PATCH-V4 1/2] drm/i915/audio: add codec wakeup override enabled/disable callback han.lu @ 2015-05-05 1:05 ` han.lu 2015-05-05 1:10 ` shuang.he 0 siblings, 1 reply; 3+ messages in thread From: han.lu @ 2015-05-05 1:05 UTC (permalink / raw) To: daniel.vetter, tiwai, jani.nikula, libin.yang, mengdong.lin, intel-gfx Cc: Lu, Han From: "Lu, Han" <han.lu@intel.com> In SKL, HDMI/DP codec and PCH HD Audio Controller are in different power wells, so it's necessary to reset display audio codecs when power well on, otherwise display audio codecs will disappear when resume from low power state. Reset steps when power on: enable codec wakeup -> azx_init_chip() -> disable codec wakeup The callback for codec wakeup enable/disable is in drivers/gpu/drm/i915/. Signed-off-by: Lu, Han <han.lu@intel.com> diff --git a/sound/pci/hda/hda_i915.c b/sound/pci/hda/hda_i915.c index 3052a2b..fe4f979a 100644 --- a/sound/pci/hda/hda_i915.c +++ b/sound/pci/hda/hda_i915.c @@ -33,6 +33,27 @@ #define AZX_REG_EM4 0x100c #define AZX_REG_EM5 0x1010 +int hda_set_codec_wakeup(struct hda_intel *hda, bool enable) +{ + struct i915_audio_component *acomp = &hda->audio_component; + + if (!acomp->ops) + return -ENODEV; + + if (!acomp->ops->codec_wake_override) { + dev_warn(&hda->chip.pci->dev, + "Invalid codec wake callback\n"); + return 0; + } + + dev_dbg(&hda->chip.pci->dev, "%s codec wakeup\n", + enable ? "enable" : "disable"); + + acomp->ops->codec_wake_override(acomp->dev, enable); + + return 0; +} + int hda_display_power(struct hda_intel *hda, bool enable) { struct i915_audio_component *acomp = &hda->audio_component; diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index 34040d2..f4ed12d 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -491,6 +491,17 @@ static void azx_init_pci(struct azx *chip) } } +static void hda_intel_init_chip(struct azx *chip, bool full_reset) +{ + struct hda_intel *hda = container_of(chip, struct hda_intel, chip); + + if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) + hda_set_codec_wakeup(hda, true); + azx_init_chip(chip, full_reset); + if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) + hda_set_codec_wakeup(hda, false); +} + /* calculate runtime delay from LPIB */ static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, unsigned int pos) @@ -827,7 +838,7 @@ static int azx_resume(struct device *dev) return -EIO; azx_init_pci(chip); - azx_init_chip(chip, true); + hda_intel_init_chip(chip, true); snd_power_change_state(card, SNDRV_CTL_POWER_D0); return 0; @@ -888,13 +899,16 @@ static int azx_runtime_resume(struct device *dev) if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { hda_display_power(hda, true); haswell_set_bclk(hda); + /* toggle codec wakeup bit for STATESTS read */ + hda_set_codec_wakeup(hda, true); + hda_set_codec_wakeup(hda, false); } /* Read STATESTS before controller reset */ status = azx_readw(chip, STATESTS); azx_init_pci(chip); - azx_init_chip(chip, true); + hda_intel_init_chip(chip, true); bus = chip->bus; if (status && bus) { @@ -1588,7 +1602,7 @@ static int azx_first_init(struct azx *chip) haswell_set_bclk(hda); } - azx_init_chip(chip, (probe_only[dev] & 2) == 0); + hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); /* codec detection */ if (!chip->codec_mask) { diff --git a/sound/pci/hda/hda_intel.h b/sound/pci/hda/hda_intel.h index d5231f7..5d2bb07 100644 --- a/sound/pci/hda/hda_intel.h +++ b/sound/pci/hda/hda_intel.h @@ -48,11 +48,16 @@ struct hda_intel { }; #ifdef CONFIG_SND_HDA_I915 +int hda_set_codec_wakeup(struct hda_intel *hda, bool enable); int hda_display_power(struct hda_intel *hda, bool enable); void haswell_set_bclk(struct hda_intel *hda); int hda_i915_init(struct hda_intel *hda); int hda_i915_exit(struct hda_intel *hda); #else +static inline int hda_set_codec_wakeup(struct hda_intel *hda, bool enable) +{ + return 0; +} static inline int hda_display_power(struct hda_intel *hda, bool enable) { return 0; -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH-V4 2/2] ALSA:hda - reset display codec when power on 2015-05-05 1:05 ` [PATCH-V4 2/2] ALSA:hda - reset display codec when power on han.lu @ 2015-05-05 1:10 ` shuang.he 0 siblings, 0 replies; 3+ messages in thread From: shuang.he @ 2015-05-05 1:10 UTC (permalink / raw) To: shuang.he, ethan.gao, intel-gfx, han.lu Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) Task id: 6287 -------------------------------------Summary------------------------------------- Platform Delta drm-intel-nightly Series Applied PNV 276/276 276/276 ILK 302/302 302/302 SNB 316/316 316/316 IVB 264/264 264/264 BYT -5 227/227 222/227 BDW 318/318 318/318 -------------------------------------Detailed------------------------------------- Platform Test drm-intel-nightly Series Applied *BYT igt@gem_dummy_reloc_loop@render FAIL(1)PASS(18) TIMEOUT(1)PASS(1) *BYT igt@gem_exec_parse@bitmasks FAIL(1)PASS(7) DMESG_WARN(1)PASS(1) (dmesg patch applied)drm:check_crtc_state[i915]]*ERROR*mismatch_in_has_infoframe(expected#,found#)@mismatch in has_infoframe .* found WARNING:at_drivers/gpu/drm/i915/intel_display.c:#check_crtc_state[i915]()@WARNING:.* at .* check_crtc_state+0x BYT igt@gem_pipe_control_store_loop@fresh-buffer FAIL(1)TIMEOUT(10)PASS(9) TIMEOUT(1)PASS(1) *BYT igt@gem_tiled_pread FAIL(1)PASS(4) DMESG_WARN(1)PASS(1) (dmesg patch applied)drm:check_crtc_state[i915]]*ERROR*mismatch_in_has_infoframe(expected#,found#)@mismatch in has_infoframe .* found WARNING:at_drivers/gpu/drm/i915/intel_display.c:#check_crtc_state[i915]()@WARNING:.* at .* check_crtc_state+0x *BYT igt@gem_userptr_blits@forked-unsync-multifd-normal FAIL(1)PASS(2) NO_RESULT(1)PASS(1) Note: You need to pay more attention to line start with '*' _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2015-05-05 1:10 UTC | newest] Thread overview: 3+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2015-05-05 1:05 [PATCH-V4 1/2] drm/i915/audio: add codec wakeup override enabled/disable callback han.lu 2015-05-05 1:05 ` [PATCH-V4 2/2] ALSA:hda - reset display codec when power on han.lu 2015-05-05 1:10 ` shuang.he
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