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From: Imre Deak <imre.deak@intel.com>
To: Nick Hoath <nicholas.hoath@intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 2/3] drm/i915/bxt: Add WaDisableSbeCacheDispatchPortSharing
Date: Wed, 06 May 2015 14:51:47 +0300	[thread overview]
Message-ID: <1430913107.29830.10.camel@intel.com> (raw)
In-Reply-To: <5548D28A.8000205@intel.com>

On ti, 2015-05-05 at 15:24 +0100, Nick Hoath wrote:
> On 29/04/2015 13:26, Deak, Imre wrote:
> > On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote:
> >> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/i915_reg.h         | 1 +
> >>   drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++++
> >>   2 files changed, 8 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index 91eef06..d34432b 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -6318,6 +6318,7 @@ enum skl_disp_power_wells {
> >>   #define GEN7_HALF_SLICE_CHICKEN1_GT2	0xf100
> >>   #define   GEN7_MAX_PS_THREAD_DEP		(8<<12)
> >>   #define   GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE	(1<<10)
> >> +#define   GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE	(1<<4)
> >>   #define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1<<3)
> >>
> >>   #define GEN9_HALF_SLICE_CHICKEN5	0xe188
> >> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> >> index 5aad253..eebee73 100644
> >> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> >> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> >> @@ -1047,6 +1047,13 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
> >>   	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> >>   			  STALL_DOP_GATING_DISABLE);
> >>
> >> +	/* WaDisableSbeCacheDispatchPortSharing:bxt */
> >> +	if (INTEL_REVID(dev) <= BXT_REVID_B0) {
> >> +		WA_SET_BIT_MASKED(
> >> +			GEN7_HALF_SLICE_CHICKEN1,
> >> +			GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
> >> +	}
> >> +
> >
> > This looks ok, but according to the WA DB it should also be added for
> > SKL (<=F0) in gen9_init_workarounds.
> >
> 
> That would work against the concept of keeping these patches as 
> bisectable as possible - Enabling these WAs for other SoCs should be 
> done as another patch/patchset.

Ok, agreed about bisectability. But it's worth adding a code comment
about SKL or at least mention it in the commit log, so we know we have
to follow up on it. Also I'd still put this to gen9_init_workarounds
with a platform check, since you'll need to move it there anyway and so
you could reduce the diff of the follow-up patch. Either way this is:

Reviewed-by: Imre Deak <imre.deak@intel.com>


> 
> >>   	return 0;
> >>   }
> >>
> >
> >
> 


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  reply	other threads:[~2015-05-06 11:51 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-10 12:12 [PATCH 0/3] drm/i915/bxt: add workarounds Nick Hoath
2015-04-10 12:12 ` [PATCH 1/3] drm/i915/bxt: Add WaDisableThreadStallDopClockGating Nick Hoath
2015-04-29 12:16   ` Imre Deak
2015-05-04  8:32     ` Daniel Vetter
2015-04-10 12:12 ` [PATCH 2/3] drm/i915/bxt: Add WaDisableSbeCacheDispatchPortSharing Nick Hoath
2015-04-29 12:26   ` Imre Deak
2015-05-05 14:24     ` Nick Hoath
2015-05-06 11:51       ` Imre Deak [this message]
2015-05-06 14:07         ` Daniel Vetter
2015-04-10 12:12 ` [PATCH 3/3] drm/i915/bxt: Add WaForceContextSaveRestoreNonCoherent Nick Hoath
2015-04-14 11:39   ` shuang.he
2015-04-29 13:02   ` Imre Deak
2015-05-06 16:01     ` Nick Hoath
2015-05-06 16:32       ` Imre Deak
2015-05-07  6:39         ` Daniel Vetter

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