[PATCH] drm/i915: Add missing POSTING_READ()s to BXT dbuf enable sequence

[PATCH] drm/i915: Add missing POSTING_READ()s to BXT dbuf enable sequence

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Do a POSTING_READ() between the DBUF_CTL register write and the
udelay() to make sure we really wait after the register write has
happened.

Spotted while reviewing Damien's SKL cdclk patch which had the
POSTING_READ()s.

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8e21e23..5c2047b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5482,6 +5482,8 @@ void broxton_init_cdclk(struct drm_device *dev)
 	broxton_set_cdclk(dev, 624000);
 
 	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
+	POSTING_READ(DBUF_CTL);
+
 	udelay(10);
 
 	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
@@ -5493,6 +5495,8 @@ void broxton_uninit_cdclk(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
+	POSTING_READ(DBUF_CTL);
+
 	udelay(10);
 
 	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
-- 
2.0.5

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Re: [PATCH] drm/i915: Add missing POSTING_READ()s to BXT dbuf enable sequence

[Imre Deak]

On ke, 2015-05-06 at 14:28 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Do a POSTING_READ() between the DBUF_CTL register write and the
> udelay() to make sure we really wait after the register write has
> happened.
> 
> Spotted while reviewing Damien's SKL cdclk patch which had the
> POSTING_READ()s.
> 
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Yep, makes sense:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 8e21e23..5c2047b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5482,6 +5482,8 @@ void broxton_init_cdclk(struct drm_device *dev)
>  	broxton_set_cdclk(dev, 624000);
>  
>  	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> +	POSTING_READ(DBUF_CTL);
> +
>  	udelay(10);
>  
>  	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
> @@ -5493,6 +5495,8 @@ void broxton_uninit_cdclk(struct drm_device *dev)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
>  	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
> +	POSTING_READ(DBUF_CTL);
> +
>  	udelay(10);
>  
>  	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)


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Re: [PATCH] drm/i915: Add missing POSTING_READ()s to BXT dbuf enable sequence

[Daniel Vetter]

On Wed, May 06, 2015 at 03:05:04PM +0300, Imre Deak wrote:
> On ke, 2015-05-06 at 14:28 +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Do a POSTING_READ() between the DBUF_CTL register write and the
> > udelay() to make sure we really wait after the register write has
> > happened.
> > 
> > Spotted while reviewing Damien's SKL cdclk patch which had the
> > POSTING_READ()s.
> > 
> > Cc: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Yep, makes sense:
> Reviewed-by: Imre Deak <imre.deak@intel.com>

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH] drm/i915: Add missing POSTING_READ()s to BXT dbuf enable sequence

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6328
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  276/276              276/276
ILK                 -1              302/302              301/302
SNB                                  316/316              316/316
IVB                                  342/342              342/342
BYT                                  286/286              286/286
BDW                                  321/321              321/321
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*ILK  igt@kms_pipe_crc_basic@bad-source      PASS(3)      DMESG_WARN(1)PASS(1)
(dmesg patch applied)drm:drm_edid_block_valid[drm]]*ERROR*EDID_checksum_is_invalid,remainder_is@EDID checksum is .* remainder is
Note: You need to pay more attention to line start with '*'
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