[PATCH 0/9] drm/i915/bxt Enable existing workarounds for Broxton

[PATCH 0/9] drm/i915/bxt Enable existing workarounds for Broxton

[Nick Hoath]

The following patch series either enables a workaround for Broxton, marks
it as applicable to Broxton, or moves it in to the SoC specific initialisation.

v2: Split out the changes as one patch per workaround (Requested by Imre)
    Removed unused additional register.
    Cleaned up whitespace. (Imre)
    Cleaned up revision ID usage (Imre)

Nick Hoath (9):
  drm/i915/bxt: Mark WaDisablePartialInstShootdown as for Broxton also.
  drm/i915/bxt: Mark workaround as for Skylake & Broxton
  drm/i915/bxt: Enable WaDisableDgMirrorFixInHalfSliceChicken5 for
    Broxton
  drm/i915/bxt: Enable
    WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken for Broxton
  drm/i915/bxt: Enable WaEnableYV12BugFixInHalfSliceChicken7 for Broxton
  drm/i915/bxt: Move WaForceEnableNonCoherent to Skylake only
  drm/i915/bxt: Mark Wa4x4STCOptimizationDisable as for Broxton also.
  drm/i915/bxt: Mark WaDisablePartialResolveInVc as for Broxton also.
  drm/i915/bxt: Mark WaCcsTlbPrefetchDisable as for Broxton also.

 drivers/gpu/drm/i915/intel_ringbuffer.c | 49 +++++++++++++++++----------------
 1 file changed, 26 insertions(+), 23 deletions(-)

-- 
2.1.1

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[PATCH 1/9] drm/i915/bxt: Mark WaDisablePartialInstShootdown as for Broxton also.

[Nick Hoath]

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 7ef9a29..49e4610 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -919,7 +919,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 	struct drm_device *dev = ring->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	/* WaDisablePartialInstShootdown:skl */
+	/* WaDisablePartialInstShootdown:skl,bxt */
 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 
-- 
2.1.1

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[PATCH 2/9] drm/i915/bxt: Mark workaround as for Skylake & Broxton

[Nick Hoath]

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 49e4610..cdbdf49 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -923,7 +923,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 
-	/* Syncing dependencies between camera and graphics */
+	/* Syncing dependencies between camera and graphics:skl,bxt */
 	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 			  GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 
-- 
2.1.1

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[PATCH 3/9] drm/i915/bxt: Enable WaDisableDgMirrorFixInHalfSliceChicken5 for Broxton

[Nick Hoath]

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index cdbdf49..3f1a784 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -927,9 +927,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 			  GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 
-	if (INTEL_REVID(dev) == SKL_REVID_A0 ||
-	    INTEL_REVID(dev) == SKL_REVID_B0) {
-		/* WaDisableDgMirrorFixInHalfSliceChicken5:skl */
+	if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
+	    INTEL_REVID(dev) == SKL_REVID_B0)) ||
+	    (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
+		/* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
 		WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 				  GEN9_DG_MIRROR_FIX_ENABLE);
 	}
-- 
2.1.1

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[PATCH 4/9] drm/i915/bxt: Enable WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken for Broxton

[Nick Hoath]

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3f1a784..ac1ad44 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -935,8 +935,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 				  GEN9_DG_MIRROR_FIX_ENABLE);
 	}
 
-	if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) {
-		/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl */
+	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
+	    (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
+		/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 		WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 				  GEN9_RHWO_OPTIMIZATION_DISABLE);
 		WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
-- 
2.1.1

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[PATCH 5/9] drm/i915/bxt: Enable WaEnableYV12BugFixInHalfSliceChicken7 for Broxton

[Nick Hoath]

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ac1ad44..076d3e5 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -944,8 +944,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 				  DISABLE_PIXEL_MASK_CAMMING);
 	}
 
-	if (INTEL_REVID(dev) >= SKL_REVID_C0) {
-		/* WaEnableYV12BugFixInHalfSliceChicken7:skl */
+	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
+	    IS_BROXTON(dev)) {
+		/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
 		WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 				  GEN9_ENABLE_YV12_BUGFIX);
 	}
-- 
2.1.1

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[PATCH 6/9] drm/i915/bxt: Move WaForceEnableNonCoherent to Skylake only

[Nick Hoath]

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 076d3e5..dec0e74 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -951,17 +951,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 				  GEN9_ENABLE_YV12_BUGFIX);
 	}
 
-	if (INTEL_REVID(dev) <= SKL_REVID_D0) {
-		/*
-		 *Use Force Non-Coherent whenever executing a 3D context. This
-		 * is a workaround for a possible hang in the unlikely event
-		 * a TLB invalidation occurs during a PSD flush.
-		 */
-		/* WaForceEnableNonCoherent:skl */
-		WA_SET_BIT_MASKED(HDC_CHICKEN0,
-				  HDC_FORCE_NON_COHERENT);
-	}
-
 	/* Wa4x4STCOptimizationDisable:skl */
 	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 
@@ -1039,6 +1028,17 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
 		WA_SET_BIT_MASKED(HIZ_CHICKEN,
 				  BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
 
+	if (INTEL_REVID(dev) <= SKL_REVID_D0) {
+		/*
+		 *Use Force Non-Coherent whenever executing a 3D context. This
+		 * is a workaround for a possible hang in the unlikely event
+		 * a TLB invalidation occurs during a PSD flush.
+		 */
+		/* WaForceEnableNonCoherent:skl */
+		WA_SET_BIT_MASKED(HDC_CHICKEN0,
+				  HDC_FORCE_NON_COHERENT);
+	}
+
 	return skl_tune_iz_hashing(ring);
 }
 
-- 
2.1.1

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[PATCH 7/9] drm/i915/bxt: Mark Wa4x4STCOptimizationDisable as for Broxton also.

[Nick Hoath]

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index dec0e74..cf36c6b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -951,7 +951,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 				  GEN9_ENABLE_YV12_BUGFIX);
 	}
 
-	/* Wa4x4STCOptimizationDisable:skl */
+	/* Wa4x4STCOptimizationDisable:skl,bxt */
 	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 
 	/* WaDisablePartialResolveInVc:skl */
-- 
2.1.1

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[PATCH 8/9] drm/i915/bxt: Mark WaDisablePartialResolveInVc as for Broxton also.

[Nick Hoath]

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index cf36c6b..e5c9f9a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -954,7 +954,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 	/* Wa4x4STCOptimizationDisable:skl,bxt */
 	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 
-	/* WaDisablePartialResolveInVc:skl */
+	/* WaDisablePartialResolveInVc:skl,bxt */
 	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
 
 	/* WaCcsTlbPrefetchDisable:skl */
-- 
2.1.1

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[PATCH 9/9] drm/i915/bxt: Mark WaCcsTlbPrefetchDisable as for Broxton also.

[Nick Hoath]

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e5c9f9a..001343f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -957,7 +957,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 	/* WaDisablePartialResolveInVc:skl,bxt */
 	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
 
-	/* WaCcsTlbPrefetchDisable:skl */
+	/* WaCcsTlbPrefetchDisable:skl,bxt */
 	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 			  GEN9_CCS_TLB_PREFETCH_ENABLE);
 
-- 
2.1.1

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Re: [PATCH 0/9] drm/i915/bxt Enable existing workarounds for Broxton

[Imre Deak]

On to, 2015-05-07 at 14:15 +0100, Nick Hoath wrote:
> The following patch series either enables a workaround for Broxton, marks
> it as applicable to Broxton, or moves it in to the SoC specific initialisation.
> 
> v2: Split out the changes as one patch per workaround (Requested by Imre)
>     Removed unused additional register.
>     Cleaned up whitespace. (Imre)
>     Cleaned up revision ID usage (Imre)
> 
> Nick Hoath (9):
>   drm/i915/bxt: Mark WaDisablePartialInstShootdown as for Broxton also.
>   drm/i915/bxt: Mark workaround as for Skylake & Broxton
>   drm/i915/bxt: Enable WaDisableDgMirrorFixInHalfSliceChicken5 for
>     Broxton
>   drm/i915/bxt: Enable
>     WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken for Broxton
>   drm/i915/bxt: Enable WaEnableYV12BugFixInHalfSliceChicken7 for Broxton
>   drm/i915/bxt: Move WaForceEnableNonCoherent to Skylake only
>   drm/i915/bxt: Mark Wa4x4STCOptimizationDisable as for Broxton also.
>   drm/i915/bxt: Mark WaDisablePartialResolveInVc as for Broxton also.
>   drm/i915/bxt: Mark WaCcsTlbPrefetchDisable as for Broxton also.
> 
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 49 +++++++++++++++++----------------
>  1 file changed, 26 insertions(+), 23 deletions(-)

Looks ok, on the patchset:
Reviewed-by: Imre Deak <imre.deak@intel.com>


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Re: [PATCH 0/9] drm/i915/bxt Enable existing workarounds for Broxton

[Daniel Vetter]

On Thu, May 07, 2015 at 06:17:03PM +0300, Imre Deak wrote:
> On to, 2015-05-07 at 14:15 +0100, Nick Hoath wrote:
> > The following patch series either enables a workaround for Broxton, marks
> > it as applicable to Broxton, or moves it in to the SoC specific initialisation.
> > 
> > v2: Split out the changes as one patch per workaround (Requested by Imre)
> >     Removed unused additional register.
> >     Cleaned up whitespace. (Imre)
> >     Cleaned up revision ID usage (Imre)
> > 
> > Nick Hoath (9):
> >   drm/i915/bxt: Mark WaDisablePartialInstShootdown as for Broxton also.
> >   drm/i915/bxt: Mark workaround as for Skylake & Broxton
> >   drm/i915/bxt: Enable WaDisableDgMirrorFixInHalfSliceChicken5 for
> >     Broxton
> >   drm/i915/bxt: Enable
> >     WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken for Broxton
> >   drm/i915/bxt: Enable WaEnableYV12BugFixInHalfSliceChicken7 for Broxton
> >   drm/i915/bxt: Move WaForceEnableNonCoherent to Skylake only
> >   drm/i915/bxt: Mark Wa4x4STCOptimizationDisable as for Broxton also.
> >   drm/i915/bxt: Mark WaDisablePartialResolveInVc as for Broxton also.
> >   drm/i915/bxt: Mark WaCcsTlbPrefetchDisable as for Broxton also.
> > 
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 49 +++++++++++++++++----------------
> >  1 file changed, 26 insertions(+), 23 deletions(-)
> 
> Looks ok, on the patchset:
> Reviewed-by: Imre Deak <imre.deak@intel.com>

Entire series merged, thanks.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 9/9] drm/i915/bxt: Mark WaCcsTlbPrefetchDisable as for Broxton also.

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6345
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  276/276              276/276
ILK                                  302/302              302/302
SNB                                  316/316              316/316
IVB                                  342/342              342/342
BYT                                  286/286              286/286
BDW                                  321/321              321/321
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
Note: You need to pay more attention to line start with '*'
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