[PATCH] drm/i915/skl: Handle eDP from generic crtc_compute_clock vfunc

[PATCH] drm/i915/skl: Handle eDP from generic crtc_compute_clock vfunc

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Since commit 4978cc93d9ac240b435ce60431aef24239b4c270 started clearing
dpll state and recomputing it via crtc_compute_clock (and probably some
other commit which triggered pipe config checking), modesetting is now
constantly triggering warnings about dpll_hw_state.ctrl1 mismatch.

Reason is crtc_compute_clock calls skl_ddi_pll_select which does not do
anything for eDP, leaving the ctrl1 state at the default of zero.

This potentially hacky fix makes skl_ddi_pll_select call
skl_edp_set_pll_config which fixes the problem for me.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---

Big CC list so no one misses the chance of saying how this is not the
right fix. :) But that is OK, I was just annoyed by the constant stream
of warnings obscuring real problems.
---
 drivers/gpu/drm/i915/intel_ddi.c | 4 +++-
 drivers/gpu/drm/i915/intel_dp.c  | 2 +-
 drivers/gpu/drm/i915/intel_drv.h | 3 +++
 3 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 807e15d..e5b7723 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1306,8 +1306,10 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
 		}
 
 		cfgcr1 = cfgcr2 = 0;
-	} else /* eDP */
+	} else /* eDP */ {
+		skl_edp_set_pll_config(crtc_state, clock);
 		return true;
+	}
 
 	crtc_state->dpll_hw_state.ctrl1 = ctrl1;
 	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 75bccd6..13b5b0e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1092,7 +1092,7 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector)
 	intel_connector_unregister(intel_connector);
 }
 
-static void
+void
 skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
 {
 	u32 ctrl1;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index aa77af7..6e26644 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1193,6 +1193,9 @@ void intel_edp_drrs_invalidate(struct drm_device *dev,
 		unsigned frontbuffer_bits);
 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
 
+void
+skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock);
+
 /* intel_dp_mst.c */
 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
-- 
2.4.0

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Re: [PATCH] drm/i915/skl: Handle eDP from generic crtc_compute_clock vfunc

[Damien Lespiau]

On Wed, May 13, 2015 at 05:40:44PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Since commit 4978cc93d9ac240b435ce60431aef24239b4c270 started clearing
> dpll state and recomputing it via crtc_compute_clock (and probably some
> other commit which triggered pipe config checking), modesetting is now
> constantly triggering warnings about dpll_hw_state.ctrl1 mismatch.
> 
> Reason is crtc_compute_clock calls skl_ddi_pll_select which does not do
> anything for eDP, leaving the ctrl1 state at the default of zero.
> 
> This potentially hacky fix makes skl_ddi_pll_select call
> skl_edp_set_pll_config which fixes the problem for me.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Damien Lespiau <damien.lespiau@intel.com>
> Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>

Nop! (at least I really don't think so).

As discussed on IRC, on DDI platforms, the (e)DP compute_config() does
the private DPLL selection, and the ddi_pll_select() does the the same
for shared DPLLs (I'm not saying that the end result we want, just how
it works today). That split comes from the introduction of shared_dpll
in the DDI PLL selection last summer.

Anyway, this means that, for SKL, dpll_hw_state is touched by the
encoder's compute_config() for (e)DP.

I think we could just remove the memset() in 4978cc93 (maybe?), or try
to unify a bit better and only have one place where we do PLL selection
(which I assume is part of the bigger atomic plan). Not
skl_edp_set_pll_config() in both compute_config() and ddi_pll_select()
though.

-- 
Damien

> ---
> 
> Big CC list so no one misses the chance of saying how this is not the
> right fix. :) But that is OK, I was just annoyed by the constant stream
> of warnings obscuring real problems.
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 4 +++-
>  drivers/gpu/drm/i915/intel_dp.c  | 2 +-
>  drivers/gpu/drm/i915/intel_drv.h | 3 +++
>  3 files changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 807e15d..e5b7723 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1306,8 +1306,10 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
>  		}
>  
>  		cfgcr1 = cfgcr2 = 0;
> -	} else /* eDP */
> +	} else /* eDP */ {
> +		skl_edp_set_pll_config(crtc_state, clock);
>  		return true;
> +	}
>  
>  	crtc_state->dpll_hw_state.ctrl1 = ctrl1;
>  	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 75bccd6..13b5b0e 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1092,7 +1092,7 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector)
>  	intel_connector_unregister(intel_connector);
>  }
>  
> -static void
> +void
>  skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
>  {
>  	u32 ctrl1;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index aa77af7..6e26644 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1193,6 +1193,9 @@ void intel_edp_drrs_invalidate(struct drm_device *dev,
>  		unsigned frontbuffer_bits);
>  void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
>  
> +void
> +skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock);
> +
>  /* intel_dp_mst.c */
>  int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
>  void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
> -- 
> 2.4.0
> 
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Re: [PATCH] drm/i915/skl: Handle eDP from generic crtc_compute_clock vfunc

[Damien Lespiau]

On Wed, May 13, 2015 at 05:56:17PM +0100, Damien Lespiau wrote:
> On Wed, May 13, 2015 at 05:40:44PM +0100, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > 
> > Since commit 4978cc93d9ac240b435ce60431aef24239b4c270 started clearing
> > dpll state and recomputing it via crtc_compute_clock (and probably some
> > other commit which triggered pipe config checking), modesetting is now
> > constantly triggering warnings about dpll_hw_state.ctrl1 mismatch.
> > 
> > Reason is crtc_compute_clock calls skl_ddi_pll_select which does not do
> > anything for eDP, leaving the ctrl1 state at the default of zero.
> > 
> > This potentially hacky fix makes skl_ddi_pll_select call
> > skl_edp_set_pll_config which fixes the problem for me.
> > 
> > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Damien Lespiau <damien.lespiau@intel.com>
> > Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Nop! (at least I really don't think so).
> 
> As discussed on IRC, on DDI platforms, the (e)DP compute_config() does
> the private DPLL selection, and the ddi_pll_select() does the the same
> for shared DPLLs (I'm not saying that the end result we want, just how
> it works today). That split comes from the introduction of shared_dpll
> in the DDI PLL selection last summer.
> 
> Anyway, this means that, for SKL, dpll_hw_state is touched by the
> encoder's compute_config() for (e)DP.
> 
> I think we could just remove the memset() in 4978cc93 (maybe?), or try
> to unify a bit better and only have one place where we do PLL selection
> (which I assume is part of the bigger atomic plan). Not
> skl_edp_set_pll_config() in both compute_config() and ddi_pll_select()
> though.

To be more precise:

commit 4978cc93d9ac240b435ce60431aef24239b4c270
Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Date:   Tue Apr 21 17:13:21 2015 +0300

    drm/i915: Preserve shared DPLL information in new pipe_config
    
    When a new pipe_config is calculated, the fields related to shared dplls
    are reset, under the assumption that they will be recalculated as part
    of the modeset, which is true with the current state of the code.
    
    As we convert to atomic, however, it will be possible to calculate a new
    pipe_config and skip the modeset. In that case, after the state swap we
    still want the shared dplls to be preserved.

Except that dpll_hw_state is not just for shared DPLLs. So maybe dpll_hw_state
shouldn't be preserved (in clear_intel_crtc_state() in the case where
shared_dpll is DPLL_ID_PRIVATE?

Note that ddi_pll_sel is also a field set by the DDI PLL selection code you may
want to preserve in clear_intel_crtc_state().

-- 
Damien
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Re: [PATCH] drm/i915/skl: Handle eDP from generic crtc_compute_clock vfunc

[Ander Conselvan De Oliveira]

On Wed, 2015-05-13 at 18:25 +0100, Damien Lespiau wrote:
> On Wed, May 13, 2015 at 05:56:17PM +0100, Damien Lespiau wrote:
> > On Wed, May 13, 2015 at 05:40:44PM +0100, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > 
> > > Since commit 4978cc93d9ac240b435ce60431aef24239b4c270 started clearing
> > > dpll state and recomputing it via crtc_compute_clock (and probably some
> > > other commit which triggered pipe config checking), modesetting is now
> > > constantly triggering warnings about dpll_hw_state.ctrl1 mismatch.
> > > 
> > > Reason is crtc_compute_clock calls skl_ddi_pll_select which does not do
> > > anything for eDP, leaving the ctrl1 state at the default of zero.
> > > 
> > > This potentially hacky fix makes skl_ddi_pll_select call
> > > skl_edp_set_pll_config which fixes the problem for me.
> > > 
> > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > Cc: Damien Lespiau <damien.lespiau@intel.com>
> > > Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Nop! (at least I really don't think so).
> > 
> > As discussed on IRC, on DDI platforms, the (e)DP compute_config() does
> > the private DPLL selection, and the ddi_pll_select() does the the same
> > for shared DPLLs (I'm not saying that the end result we want, just how
> > it works today). That split comes from the introduction of shared_dpll
> > in the DDI PLL selection last summer.
> > 
> > Anyway, this means that, for SKL, dpll_hw_state is touched by the
> > encoder's compute_config() for (e)DP.
> > 
> > I think we could just remove the memset() in 4978cc93 (maybe?), or try
> > to unify a bit better and only have one place where we do PLL selection
> > (which I assume is part of the bigger atomic plan). Not
> > skl_edp_set_pll_config() in both compute_config() and ddi_pll_select()
> > though.
> 
> To be more precise:
> 
> commit 4978cc93d9ac240b435ce60431aef24239b4c270
> Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> Date:   Tue Apr 21 17:13:21 2015 +0300
> 
>     drm/i915: Preserve shared DPLL information in new pipe_config
>     
>     When a new pipe_config is calculated, the fields related to shared dplls
>     are reset, under the assumption that they will be recalculated as part
>     of the modeset, which is true with the current state of the code.
>     
>     As we convert to atomic, however, it will be possible to calculate a new
>     pipe_config and skip the modeset. In that case, after the state swap we
>     still want the shared dplls to be preserved.
> 
> Except that dpll_hw_state is not just for shared DPLLs. So maybe dpll_hw_state
> shouldn't be preserved (in clear_intel_crtc_state() in the case where
> shared_dpll is DPLL_ID_PRIVATE?

The idea here is that when the modeset code does a flip only, we are
still doing a state swap. Before the swap was in place, we simply
wouldn't change the pipe_config, so the value for dpll_hw_state wouldn't
change either. If there is an actual modeset these values are
recalculated, so preserving the state should be harmless.


> Note that ddi_pll_sel is also a field set by the DDI PLL selection code you may
> want to preserve in clear_intel_crtc_state().

Yeah, I missed that one. We *definitely* want to preserve it. I'll send
a patch for doing that shortly.

Thanks,
Ander

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Re: [PATCH] drm/i915/skl: Handle eDP from generic crtc_compute_clock vfunc

[Ander Conselvan De Oliveira]

On Wed, 2015-05-13 at 17:56 +0100, Damien Lespiau wrote:
> On Wed, May 13, 2015 at 05:40:44PM +0100, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > 
> > Since commit 4978cc93d9ac240b435ce60431aef24239b4c270 started clearing
> > dpll state and recomputing it via crtc_compute_clock (and probably some
> > other commit which triggered pipe config checking), modesetting is now
> > constantly triggering warnings about dpll_hw_state.ctrl1 mismatch.
> > 
> > Reason is crtc_compute_clock calls skl_ddi_pll_select which does not do
> > anything for eDP, leaving the ctrl1 state at the default of zero.
> > 
> > This potentially hacky fix makes skl_ddi_pll_select call
> > skl_edp_set_pll_config which fixes the problem for me.
> > 
> > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Damien Lespiau <damien.lespiau@intel.com>
> > Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Nop! (at least I really don't think so).
> 
> As discussed on IRC, on DDI platforms, the (e)DP compute_config() does
> the private DPLL selection, and the ddi_pll_select() does the the same
> for shared DPLLs (I'm not saying that the end result we want, just how
> it works today). That split comes from the introduction of shared_dpll
> in the DDI PLL selection last summer.
> 
> Anyway, this means that, for SKL, dpll_hw_state is touched by the
> encoder's compute_config() for (e)DP.
> 
> I think we could just remove the memset() in 4978cc93 (maybe?), or try
> to unify a bit better and only have one place where we do PLL selection
> (which I assume is part of the bigger atomic plan). Not
> skl_edp_set_pll_config() in both compute_config() and ddi_pll_select()
> though.

The memset() was added to fix a similar warning on a different platform,
but I can't remember which one now. Perhaps a more immediate fix would
be to move the memset() down the call chain.

Long term I think we should remove all the assumptions of initial values
from the compute config path. Having only one place that selects PLL
would also be nice IMO.

Ander


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[PATCH] drm/i915: Don't overwrite (e)DP PLL selection on SKL

[Ander Conselvan de Oliveira]

In the following commit, the place where the contents of dpll_hw_state
in crtc_state where zeroed was changed. Prior to that commit, it
happened when the new state was allocated, but now that happens just
before the call the .crtc_compute_clock() hook. The DP code for SKL,
however, sets up the (private) PLL in the encoder compute config
function that has already run by the time that memset() is reached,
causing the previous value to be lost.

This patch fixes the issue by moving the memset() down the call chain,
so that it is only called if the values in dpll_hw_state are going to be
updated.

commit 4978cc93d9ac240b435ce60431aef24239b4c270
Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Date:   Tue Apr 21 17:13:21 2015 +0300

    drm/i915: Preserve shared DPLL information in new pipe_config

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90462
---

On Fri, 2015-05-15 at 13:31 +0300, Ander Conselvan De Oliveira wrote:
> The memset() was added to fix a similar warning on a different platform,
> but I can't remember which one now. Perhaps a more immediate fix would
> be to move the memset() down the call chain.

Like this completely untested patch.

---
 drivers/gpu/drm/i915/intel_ddi.c     | 9 +++++++++
 drivers/gpu/drm/i915/intel_display.c | 8 ++++++--
 drivers/gpu/drm/i915/intel_dp.c      | 3 +++
 3 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ec5d2ea..48d45b2 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1087,6 +1087,9 @@ hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
 		      WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 		      WRPLL_DIVIDER_POST(p);
 
+		memset(&crtc_state->dpll_hw_state, 0,
+		       sizeof(crtc_state->dpll_hw_state));
+
 		crtc_state->dpll_hw_state.wrpll = val;
 
 		pll = intel_get_shared_dpll(intel_crtc, crtc_state);
@@ -1309,6 +1312,9 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
 	} else /* eDP */
 		return true;
 
+	memset(&crtc_state->dpll_hw_state, 0,
+	       sizeof(crtc_state->dpll_hw_state));
+
 	crtc_state->dpll_hw_state.ctrl1 = ctrl1;
 	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
 	crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
@@ -1419,6 +1425,9 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
 		}
 	}
 
+	memset(&crtc_state->dpll_hw_state, 0,
+	       sizeof(crtc_state->dpll_hw_state));
+
 	crtc_state->dpll_hw_state.ebb0 =
 		PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
 	crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8d40d7d..a7732b4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7475,6 +7475,9 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
 	struct drm_connector_state *connector_state;
 	int i;
 
+	memset(&crtc_state->dpll_hw_state, 0,
+	       sizeof(crtc_state->dpll_hw_state));
+
 	for_each_connector_in_state(state, connector, connector_state, i) {
 		if (connector_state->crtc != &crtc->base)
 			continue;
@@ -8516,6 +8519,9 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
 	bool is_lvds = false;
 	struct intel_shared_dpll *pll;
 
+	memset(&crtc_state->dpll_hw_state, 0,
+	       sizeof(crtc_state->dpll_hw_state));
+
 	is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
 
 	WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
@@ -12265,8 +12271,6 @@ static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
 		if (needs_modeset(crtc_state)) {
 			clear_pipes |= 1 << intel_crtc->pipe;
 			intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
-			memset(&intel_crtc_state->dpll_hw_state, 0,
-			       sizeof(intel_crtc_state->dpll_hw_state));
 		}
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5bd73ad..6fd9c60 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1097,6 +1097,9 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
 {
 	u32 ctrl1;
 
+	memset(&pipe_config->dpll_hw_state, 0,
+	       sizeof(pipe_config->dpll_hw_state));
+
 	pipe_config->ddi_pll_sel = SKL_DPLL0;
 	pipe_config->dpll_hw_state.cfgcr1 = 0;
 	pipe_config->dpll_hw_state.cfgcr2 = 0;
-- 
2.1.0

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Re: [PATCH] drm/i915: Don't overwrite (e)DP PLL selection on SKL

[Jani Nikula]

On Fri, 15 May 2015, Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> wrote:
> In the following commit, the place where the contents of dpll_hw_state
> in crtc_state where zeroed was changed. Prior to that commit, it
> happened when the new state was allocated, but now that happens just
> before the call the .crtc_compute_clock() hook. The DP code for SKL,
> however, sets up the (private) PLL in the encoder compute config
> function that has already run by the time that memset() is reached,
> causing the previous value to be lost.
>
> This patch fixes the issue by moving the memset() down the call chain,
> so that it is only called if the values in dpll_hw_state are going to be
> updated.
>
> commit 4978cc93d9ac240b435ce60431aef24239b4c270
> Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> Date:   Tue Apr 21 17:13:21 2015 +0300
>
>     drm/i915: Preserve shared DPLL information in new pipe_config
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90462
> ---
>
> On Fri, 2015-05-15 at 13:31 +0300, Ander Conselvan De Oliveira wrote:
>> The memset() was added to fix a similar warning on a different platform,
>> but I can't remember which one now. Perhaps a more immediate fix would
>> be to move the memset() down the call chain.
>
> Like this completely untested patch.

Missing sob.

Jani.

>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c     | 9 +++++++++
>  drivers/gpu/drm/i915/intel_display.c | 8 ++++++--
>  drivers/gpu/drm/i915/intel_dp.c      | 3 +++
>  3 files changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index ec5d2ea..48d45b2 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1087,6 +1087,9 @@ hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
>  		      WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
>  		      WRPLL_DIVIDER_POST(p);
>  
> +		memset(&crtc_state->dpll_hw_state, 0,
> +		       sizeof(crtc_state->dpll_hw_state));
> +
>  		crtc_state->dpll_hw_state.wrpll = val;
>  
>  		pll = intel_get_shared_dpll(intel_crtc, crtc_state);
> @@ -1309,6 +1312,9 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
>  	} else /* eDP */
>  		return true;
>  
> +	memset(&crtc_state->dpll_hw_state, 0,
> +	       sizeof(crtc_state->dpll_hw_state));
> +
>  	crtc_state->dpll_hw_state.ctrl1 = ctrl1;
>  	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
>  	crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
> @@ -1419,6 +1425,9 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>  		}
>  	}
>  
> +	memset(&crtc_state->dpll_hw_state, 0,
> +	       sizeof(crtc_state->dpll_hw_state));
> +
>  	crtc_state->dpll_hw_state.ebb0 =
>  		PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
>  	crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 8d40d7d..a7732b4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7475,6 +7475,9 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
>  	struct drm_connector_state *connector_state;
>  	int i;
>  
> +	memset(&crtc_state->dpll_hw_state, 0,
> +	       sizeof(crtc_state->dpll_hw_state));
> +
>  	for_each_connector_in_state(state, connector, connector_state, i) {
>  		if (connector_state->crtc != &crtc->base)
>  			continue;
> @@ -8516,6 +8519,9 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
>  	bool is_lvds = false;
>  	struct intel_shared_dpll *pll;
>  
> +	memset(&crtc_state->dpll_hw_state, 0,
> +	       sizeof(crtc_state->dpll_hw_state));
> +
>  	is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
>  
>  	WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
> @@ -12265,8 +12271,6 @@ static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
>  		if (needs_modeset(crtc_state)) {
>  			clear_pipes |= 1 << intel_crtc->pipe;
>  			intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
> -			memset(&intel_crtc_state->dpll_hw_state, 0,
> -			       sizeof(intel_crtc_state->dpll_hw_state));
>  		}
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 5bd73ad..6fd9c60 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1097,6 +1097,9 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
>  {
>  	u32 ctrl1;
>  
> +	memset(&pipe_config->dpll_hw_state, 0,
> +	       sizeof(pipe_config->dpll_hw_state));
> +
>  	pipe_config->ddi_pll_sel = SKL_DPLL0;
>  	pipe_config->dpll_hw_state.cfgcr1 = 0;
>  	pipe_config->dpll_hw_state.cfgcr2 = 0;
> -- 
> 2.1.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH] drm/i915: Don't overwrite (e)DP PLL selection on SKL

[Ander Conselvan De Oliveira]

On Fri, 2015-05-15 at 13:56 +0300, Jani Nikula wrote:
> On Fri, 15 May 2015, Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> wrote:
> > In the following commit, the place where the contents of dpll_hw_state
> > in crtc_state where zeroed was changed. Prior to that commit, it
> > happened when the new state was allocated, but now that happens just
> > before the call the .crtc_compute_clock() hook. The DP code for SKL,
> > however, sets up the (private) PLL in the encoder compute config
> > function that has already run by the time that memset() is reached,
> > causing the previous value to be lost.
> >
> > This patch fixes the issue by moving the memset() down the call chain,
> > so that it is only called if the values in dpll_hw_state are going to be
> > updated.
> >
> > commit 4978cc93d9ac240b435ce60431aef24239b4c270
> > Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> > Date:   Tue Apr 21 17:13:21 2015 +0300
> >
> >     drm/i915: Preserve shared DPLL information in new pipe_config
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90462
> > ---
> >
> > On Fri, 2015-05-15 at 13:31 +0300, Ander Conselvan De Oliveira wrote:
> >> The memset() was added to fix a similar warning on a different platform,
> >> but I can't remember which one now. Perhaps a more immediate fix would
> >> be to move the memset() down the call chain.
> >
> > Like this completely untested patch.
> 
> Missing sob.

Oops.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

> 
> Jani.
> 
> >
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c     | 9 +++++++++
> >  drivers/gpu/drm/i915/intel_display.c | 8 ++++++--
> >  drivers/gpu/drm/i915/intel_dp.c      | 3 +++
> >  3 files changed, 18 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index ec5d2ea..48d45b2 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1087,6 +1087,9 @@ hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
> >  		      WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
> >  		      WRPLL_DIVIDER_POST(p);
> >  
> > +		memset(&crtc_state->dpll_hw_state, 0,
> > +		       sizeof(crtc_state->dpll_hw_state));
> > +
> >  		crtc_state->dpll_hw_state.wrpll = val;
> >  
> >  		pll = intel_get_shared_dpll(intel_crtc, crtc_state);
> > @@ -1309,6 +1312,9 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
> >  	} else /* eDP */
> >  		return true;
> >  
> > +	memset(&crtc_state->dpll_hw_state, 0,
> > +	       sizeof(crtc_state->dpll_hw_state));
> > +
> >  	crtc_state->dpll_hw_state.ctrl1 = ctrl1;
> >  	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
> >  	crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
> > @@ -1419,6 +1425,9 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
> >  		}
> >  	}
> >  
> > +	memset(&crtc_state->dpll_hw_state, 0,
> > +	       sizeof(crtc_state->dpll_hw_state));
> > +
> >  	crtc_state->dpll_hw_state.ebb0 =
> >  		PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
> >  	crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 8d40d7d..a7732b4 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -7475,6 +7475,9 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
> >  	struct drm_connector_state *connector_state;
> >  	int i;
> >  
> > +	memset(&crtc_state->dpll_hw_state, 0,
> > +	       sizeof(crtc_state->dpll_hw_state));
> > +
> >  	for_each_connector_in_state(state, connector, connector_state, i) {
> >  		if (connector_state->crtc != &crtc->base)
> >  			continue;
> > @@ -8516,6 +8519,9 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
> >  	bool is_lvds = false;
> >  	struct intel_shared_dpll *pll;
> >  
> > +	memset(&crtc_state->dpll_hw_state, 0,
> > +	       sizeof(crtc_state->dpll_hw_state));
> > +
> >  	is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
> >  
> >  	WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
> > @@ -12265,8 +12271,6 @@ static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
> >  		if (needs_modeset(crtc_state)) {
> >  			clear_pipes |= 1 << intel_crtc->pipe;
> >  			intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
> > -			memset(&intel_crtc_state->dpll_hw_state, 0,
> > -			       sizeof(intel_crtc_state->dpll_hw_state));
> >  		}
> >  	}
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 5bd73ad..6fd9c60 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1097,6 +1097,9 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
> >  {
> >  	u32 ctrl1;
> >  
> > +	memset(&pipe_config->dpll_hw_state, 0,
> > +	       sizeof(pipe_config->dpll_hw_state));
> > +
> >  	pipe_config->ddi_pll_sel = SKL_DPLL0;
> >  	pipe_config->dpll_hw_state.cfgcr1 = 0;
> >  	pipe_config->dpll_hw_state.cfgcr2 = 0;
> > -- 
> > 2.1.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 


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Re: [PATCH] drm/i915: Don't overwrite (e)DP PLL selection on SKL

[Tvrtko Ursulin]

Hi,

On 05/15/2015 11:34 AM, Ander Conselvan de Oliveira wrote:
> In the following commit, the place where the contents of dpll_hw_state
> in crtc_state where zeroed was changed. Prior to that commit, it
> happened when the new state was allocated, but now that happens just
> before the call the .crtc_compute_clock() hook. The DP code for SKL,
> however, sets up the (private) PLL in the encoder compute config
> function that has already run by the time that memset() is reached,
> causing the previous value to be lost.
>
> This patch fixes the issue by moving the memset() down the call chain,
> so that it is only called if the values in dpll_hw_state are going to be
> updated.
>
> commit 4978cc93d9ac240b435ce60431aef24239b4c270
> Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> Date:   Tue Apr 21 17:13:21 2015 +0300
>
>      drm/i915: Preserve shared DPLL information in new pipe_config
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90462
> ---

I gave it a quick spin - it does fix the warnings on my system.

Regards,

Tvrtko
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Re: [PATCH] drm/i915: Don't overwrite (e)DP PLL selection on SKL

[Damien Lespiau]

On Fri, May 15, 2015 at 01:34:29PM +0300, Ander Conselvan de Oliveira wrote:
> In the following commit, the place where the contents of dpll_hw_state
> in crtc_state where zeroed was changed. Prior to that commit, it
> happened when the new state was allocated, but now that happens just
> before the call the .crtc_compute_clock() hook. The DP code for SKL,
> however, sets up the (private) PLL in the encoder compute config
> function that has already run by the time that memset() is reached,
> causing the previous value to be lost.
> 
> This patch fixes the issue by moving the memset() down the call chain,
> so that it is only called if the values in dpll_hw_state are going to be
> updated.
> 
> commit 4978cc93d9ac240b435ce60431aef24239b4c270
> Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> Date:   Tue Apr 21 17:13:21 2015 +0300
> 
>     drm/i915: Preserve shared DPLL information in new pipe_config
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90462

Looks good to me:

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
> 
> On Fri, 2015-05-15 at 13:31 +0300, Ander Conselvan De Oliveira wrote:
> > The memset() was added to fix a similar warning on a different platform,
> > but I can't remember which one now. Perhaps a more immediate fix would
> > be to move the memset() down the call chain.
> 
> Like this completely untested patch.
> 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c     | 9 +++++++++
>  drivers/gpu/drm/i915/intel_display.c | 8 ++++++--
>  drivers/gpu/drm/i915/intel_dp.c      | 3 +++
>  3 files changed, 18 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index ec5d2ea..48d45b2 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1087,6 +1087,9 @@ hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
>  		      WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
>  		      WRPLL_DIVIDER_POST(p);
>  
> +		memset(&crtc_state->dpll_hw_state, 0,
> +		       sizeof(crtc_state->dpll_hw_state));
> +
>  		crtc_state->dpll_hw_state.wrpll = val;
>  
>  		pll = intel_get_shared_dpll(intel_crtc, crtc_state);
> @@ -1309,6 +1312,9 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
>  	} else /* eDP */
>  		return true;
>  
> +	memset(&crtc_state->dpll_hw_state, 0,
> +	       sizeof(crtc_state->dpll_hw_state));
> +
>  	crtc_state->dpll_hw_state.ctrl1 = ctrl1;
>  	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
>  	crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
> @@ -1419,6 +1425,9 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>  		}
>  	}
>  
> +	memset(&crtc_state->dpll_hw_state, 0,
> +	       sizeof(crtc_state->dpll_hw_state));
> +
>  	crtc_state->dpll_hw_state.ebb0 =
>  		PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
>  	crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 8d40d7d..a7732b4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7475,6 +7475,9 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
>  	struct drm_connector_state *connector_state;
>  	int i;
>  
> +	memset(&crtc_state->dpll_hw_state, 0,
> +	       sizeof(crtc_state->dpll_hw_state));
> +
>  	for_each_connector_in_state(state, connector, connector_state, i) {
>  		if (connector_state->crtc != &crtc->base)
>  			continue;
> @@ -8516,6 +8519,9 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
>  	bool is_lvds = false;
>  	struct intel_shared_dpll *pll;
>  
> +	memset(&crtc_state->dpll_hw_state, 0,
> +	       sizeof(crtc_state->dpll_hw_state));
> +
>  	is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
>  
>  	WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
> @@ -12265,8 +12271,6 @@ static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
>  		if (needs_modeset(crtc_state)) {
>  			clear_pipes |= 1 << intel_crtc->pipe;
>  			intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
> -			memset(&intel_crtc_state->dpll_hw_state, 0,
> -			       sizeof(intel_crtc_state->dpll_hw_state));
>  		}
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 5bd73ad..6fd9c60 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1097,6 +1097,9 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
>  {
>  	u32 ctrl1;
>  
> +	memset(&pipe_config->dpll_hw_state, 0,
> +	       sizeof(pipe_config->dpll_hw_state));
> +
>  	pipe_config->ddi_pll_sel = SKL_DPLL0;
>  	pipe_config->dpll_hw_state.cfgcr1 = 0;
>  	pipe_config->dpll_hw_state.cfgcr2 = 0;
> -- 
> 2.1.0
> 
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Re: [PATCH] drm/i915: Don't overwrite (e)DP PLL selection on SKL

[Daniel Vetter]

On Fri, May 15, 2015 at 12:19:12PM +0100, Damien Lespiau wrote:
> On Fri, May 15, 2015 at 01:34:29PM +0300, Ander Conselvan de Oliveira wrote:
> > In the following commit, the place where the contents of dpll_hw_state
> > in crtc_state where zeroed was changed. Prior to that commit, it
> > happened when the new state was allocated, but now that happens just
> > before the call the .crtc_compute_clock() hook. The DP code for SKL,
> > however, sets up the (private) PLL in the encoder compute config
> > function that has already run by the time that memset() is reached,
> > causing the previous value to be lost.
> > 
> > This patch fixes the issue by moving the memset() down the call chain,
> > so that it is only called if the values in dpll_hw_state are going to be
> > updated.
> > 
> > commit 4978cc93d9ac240b435ce60431aef24239b4c270
> > Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> > Date:   Tue Apr 21 17:13:21 2015 +0300
> > 
> >     drm/i915: Preserve shared DPLL information in new pipe_config
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90462
> 
> Looks good to me:
> 
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH] drm/i915: Don't overwrite (e)DP PLL selection on SKL

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6417
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  276/276              276/276
ILK                                  302/302              302/302
SNB                 -1              314/314              313/314
IVB                                  338/338              338/338
BYT                                  286/286              286/286
BDW                                  320/320              320/320
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 SNB  igt@pm_rpm@dpms-mode-unset-non-lpsp      DMESG_WARN(16)PASS(1)      DMESG_WARN(1)
(dmesg patch applied)WARNING:at_drivers/gpu/drm/i915/intel_uncore.c:#assert_device_not_suspended[i915]()@WARNING:.* at .* assert_device_not_suspended+0x
Note: You need to pay more attention to line start with '*'
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Re: [PATCH] drm/i915/skl: Handle eDP from generic crtc_compute_clock vfunc

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6410
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  234/234              234/234
ILK                                  262/262              262/262
SNB                 -1              282/282              281/282
IVB                                  300/300              300/300
BYT                                  254/254              254/254
BDW                                  275/275              275/275
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 SNB  igt@pm_rpm@dpms-mode-unset-non-lpsp      DMESG_WARN(4)PASS(1)      DMESG_WARN(1)
(dmesg patch applied)WARNING:at_drivers/gpu/drm/i915/intel_uncore.c:#assert_device_not_suspended[i915]()@WARNING:.* at .* assert_device_not_suspended+0x
Note: You need to pay more attention to line start with '*'
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