From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>,
Mika Kuoppala <mika.kuoppala@intel.com>
Subject: [PATCH pre4/4] drm/i915/bxt: fix WaForceContextSaveRestoreNonCoherent on steppings B0+
Date: Tue, 19 May 2015 17:05:41 +0300 [thread overview]
Message-ID: <1432044342-20362-1-git-send-email-imre.deak@intel.com> (raw)
In-Reply-To: <1432037102-12945-4-git-send-email-imre.deak@intel.com>
On B0 and C0 steppings the workaround enable bit would be overriden by
default, so the overriding must be disabled.
The WA was added in
commit 83a24979c40ebbf0fa0cd14df16f74142f373cd3
Author: Nick Hoath <nicholas.hoath@intel.com>
Date: Fri Apr 10 13:12:26 2015 +0100
drm/i915/bxt: Add WaForceContextSaveRestoreNonCoherent
Spotted-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 84af255..5afff3a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5791,6 +5791,7 @@ enum skl_disp_power_wells {
/* GEN8 chicken */
#define HDC_CHICKEN0 0x7300
+#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
#define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
#define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2e342db..643fe89 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1049,6 +1049,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
{
struct drm_device *dev = ring->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ uint32_t tmp;
gen9_init_workarounds(ring);
@@ -1057,8 +1058,10 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
STALL_DOP_GATING_DISABLE);
/* WaForceContextSaveRestoreNonCoherent:bxt */
- WA_SET_BIT_MASKED(HDC_CHICKEN0,
- HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
+ tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
+ if (INTEL_REVID(dev) >= BXT_REVID_B0)
+ tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
+ WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
return 0;
}
--
2.1.4
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next prev parent reply other threads:[~2015-05-19 14:05 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-19 12:04 [PATCH 1/4] drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A Imre Deak
2015-05-19 12:05 ` [PATCH 2/4] drm/i915/skl: add F0 stepping ID Imre Deak
2015-05-19 14:42 ` Damien Lespiau
2015-05-20 7:27 ` Daniel Vetter
2015-05-19 12:05 ` [PATCH 3/4] drm/i915/skl: enable WaDisableSbeCacheDispatchPortSharing Imre Deak
2015-05-19 12:05 ` [PATCH 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent Imre Deak
2015-05-19 13:08 ` Mika Kuoppala
2015-05-19 13:28 ` Imre Deak
2015-05-19 14:05 ` Imre Deak [this message]
2015-05-19 14:05 ` [PATCH v2 " Imre Deak
2015-05-21 10:36 ` Mika Kuoppala
2015-05-21 12:02 ` Daniel Vetter
2015-05-21 7:45 ` [PATCH " shuang.he
2015-05-19 14:39 ` [PATCH 1/4] drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A Damien Lespiau
2015-05-19 14:46 ` Damien Lespiau
2015-05-19 14:52 ` Imre Deak
2015-05-19 14:56 ` Damien Lespiau
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