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From: Imre Deak <imre.deak@intel.com>
To: Damien Lespiau <damien.lespiau@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/4] drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A
Date: Tue, 19 May 2015 17:52:27 +0300	[thread overview]
Message-ID: <1432047147.30136.10.camel@intel.com> (raw)
In-Reply-To: <20150519144630.GH22560@strange.ger.corp.intel.com>

On ti, 2015-05-19 at 15:46 +0100, Damien Lespiau wrote:
> On Tue, May 19, 2015 at 03:39:25PM +0100, Damien Lespiau wrote:
> > On Tue, May 19, 2015 at 03:04:59PM +0300, Imre Deak wrote:
> > > Also make the WA comment consistent with the rest, where the stepping
> > > info is not shown.
> > > 
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++------
> > >  1 file changed, 3 insertions(+), 6 deletions(-)
> > > 
> > > [ The patchset is a follow-up to:
> > >   http://lists.freedesktop.org/archives/intel-gfx/2015-May/065989.html ]
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > index 9b96ed7..461b9be 100644
> > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > @@ -961,12 +961,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> > >  	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> > >  			  GEN9_CCS_TLB_PREFETCH_ENABLE);
> > >  
> > > -	/*
> > > -	 * FIXME: don't apply the following on BXT for stepping C. On BXT A0
> > > -	 * the flag reads back as 0.
> > > -	 */
> > > -	/* WaDisableMaskBasedCammingInRCC:sklC,bxtA */
> > > -	if (INTEL_REVID(dev) == SKL_REVID_C0 || IS_BROXTON(dev))
> > > +	/* WaDisableMaskBasedCammingInRCC:skl,bxt */
> > 
> > For the record, there seem to be some confusion in the W/A db:
> > 
> >   - The W/A seems to have been renamed to WaDisablePixelMaskBasedCammingInRcpbe
> >     and indeed there's a bit to do that, but the bug in question talks
> >     about bit 14 of 7308, which is the disabling bit for the RCC unit
> >   - The W/A isn't listed in the W/A db for BXT
> > 
> > In doubt, defaulting to trusting the spec and bug db is probably the
> > saner option, so:
> > 
> > Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
> 
> Spoke too soon. This register is in the render context so has to be
> written from the ring...

Not sure what you mean. I thought all WAs inited here are written from
the ring.

--Imre


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  reply	other threads:[~2015-05-19 14:52 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-19 12:04 [PATCH 1/4] drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A Imre Deak
2015-05-19 12:05 ` [PATCH 2/4] drm/i915/skl: add F0 stepping ID Imre Deak
2015-05-19 14:42   ` Damien Lespiau
2015-05-20  7:27     ` Daniel Vetter
2015-05-19 12:05 ` [PATCH 3/4] drm/i915/skl: enable WaDisableSbeCacheDispatchPortSharing Imre Deak
2015-05-19 12:05 ` [PATCH 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent Imre Deak
2015-05-19 13:08   ` Mika Kuoppala
2015-05-19 13:28     ` Imre Deak
2015-05-19 14:05   ` [PATCH pre4/4] drm/i915/bxt: fix WaForceContextSaveRestoreNonCoherent on steppings B0+ Imre Deak
2015-05-19 14:05   ` [PATCH v2 4/4] drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent Imre Deak
2015-05-21 10:36     ` Mika Kuoppala
2015-05-21 12:02       ` Daniel Vetter
2015-05-21  7:45   ` [PATCH " shuang.he
2015-05-19 14:39 ` [PATCH 1/4] drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A Damien Lespiau
2015-05-19 14:46   ` Damien Lespiau
2015-05-19 14:52     ` Imre Deak [this message]
2015-05-19 14:56       ` Damien Lespiau

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