From mboxrd@z Thu Jan 1 00:00:00 1970 From: jim.bride@linux.intel.com Subject: [PATCH] drm/i915/hsw: Fix workaround for server AUX channel clock divisor Date: Tue, 19 May 2015 09:13:30 -0700 Message-ID: <1432052010-13412-1-git-send-email-jim.bride@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id BEDAB6E066 for ; Tue, 19 May 2015 09:11:04 -0700 (PDT) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org RnJvbTogSmltIEJyaWRlIDxqaW0uYnJpZGVAbGludXguaW50ZWwuY29tPgoKQWNjb3JkaW5nIHRv IHRoZSBIU1cgYi1zcGVjIHdlIG5lZWQgdG8gdHJ5IGNsb2NrIGRpdmlzb3JzIG9mIDYzCmFuZCA3 MiwgZWFjaCAzIG9yIG1vcmUgdGltZXMsIHdoZW4gYXR0ZW1wdGluZyBEUCBBVVggY2hhbm5lbApj b21tdW5pY2F0aW9uIG9uIGEgc2VydmVyIGNoaXBzZXQuICBUaGlzIGFjdHVhbGx5IHdhc24ndCBo YXBwZW5pbmcKZHVlIHRvIGEgc2hvcnQtY2lyY3VpdCB0aGF0IG9ubHkgY2hlY2tlZCB0aGUgRFBf QVVYX0NIX0NUTF9ET05FIGJpdAppbiBzdGF0dXMgcmF0aGVyIHRoYW4gY2hlY2tpbmcgdGhhdCB0 aGUgb3BlcmF0aW9uIHdhcyBkb25lIGFuZAp0aGF0IERQX0FVWF9DSF9DVExfVElNRV9PVVRfRVJS T1Igd2FzIG5vdCBzZXQuCgpTaWduZWQtb2ZmLWJ5OiBKaW0gQnJpZGUgPGppbS5icmlkZUBsaW51 eC5pbnRlbC5jb20+Ci0tLQogZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZHAuYyB8IDMgKyst CiAxIGZpbGUgY2hhbmdlZCwgMiBpbnNlcnRpb25zKCspLCAxIGRlbGV0aW9uKC0pCgpkaWZmIC0t Z2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZHAuYyBiL2RyaXZlcnMvZ3B1L2RybS9p OTE1L2ludGVsX2RwLmMKaW5kZXggMGVkYzMwNS4uYzAxYTNmOSAxMDA2NDQKLS0tIGEvZHJpdmVy cy9ncHUvZHJtL2k5MTUvaW50ZWxfZHAuYworKysgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRl bF9kcC5jCkBAIC04OTUsNyArODk1LDggQEAgaW50ZWxfZHBfYXV4X2NoKHN0cnVjdCBpbnRlbF9k cCAqaW50ZWxfZHAsCiAJCQlpZiAoc3RhdHVzICYgRFBfQVVYX0NIX0NUTF9ET05FKQogCQkJCWJy ZWFrOwogCQl9Ci0JCWlmIChzdGF0dXMgJiBEUF9BVVhfQ0hfQ1RMX0RPTkUpCisJCWlmICgoc3Rh dHVzICYgRFBfQVVYX0NIX0NUTF9ET05FKSAmJgorCQkgICAgIShzdGF0dXMgJiBEUF9BVVhfQ0hf Q1RMX1RJTUVfT1VUX0VSUk9SKSkKIAkJCWJyZWFrOwogCX0KIAotLSAKMS45LjEKCl9fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCkludGVsLWdmeCBtYWlsaW5n IGxpc3QKSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwOi8vbGlzdHMuZnJlZWRl c2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg==