From: Minu Mathai <minu.mathai@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Minu <minu.mathai@intel.com>
Subject: [PATCH] drm/i915: Correcting the reg definitions for PORT_DFT
Date: Fri, 5 Jun 2015 14:00:24 +0100 [thread overview]
Message-ID: <1433509224-9502-1-git-send-email-minu.mathai@intel.com> (raw)
From: Minu <minu.mathai@intel.com>
Display CRCs were not readable because the register defintions
for PORT_DFT_I9XX and PORT_DFT2_G4X were wrong.
MMIO offset needs to be added to these register offsets to fix them.
Issue: GMINL-6869
Signed-off-by: Minu Mathai <minu.mathai@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7213224..c327c7c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3193,7 +3193,7 @@ enum skl_disp_power_wells {
#define PCH_HDMIC 0xe1150
#define PCH_HDMID 0xe1160
-#define PORT_DFT_I9XX 0x61150
+#define PORT_DFT_I9XX (dev_priv->info.display_mmio_offset + 0x61150)
#define DC_BALANCE_RESET (1 << 25)
#define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154)
#define DC_BALANCE_RESET_VLV (1 << 31)
--
1.9.1
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next reply other threads:[~2015-06-05 13:00 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-05 13:00 Minu Mathai [this message]
2015-06-05 13:08 ` [PATCH] drm/i915: Correcting the reg definitions for PORT_DFT Ville Syrjälä
2015-06-08 13:23 ` Mathai, Minu
2015-06-08 13:48 ` Jani Nikula
2015-06-09 12:06 ` Mathai, Minu
2015-06-09 12:16 ` Ville Syrjälä
2015-06-09 13:32 ` Mathai, Minu
2015-06-09 15:01 ` Dave Gordon
2015-06-09 15:24 ` Ville Syrjälä
2015-06-10 8:09 ` Jani Nikula
2015-06-10 12:27 ` Dave Gordon
2015-06-10 12:50 ` Jani Nikula
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