[PATCH 0/2] drm/i915/bxt: work around HW coherency issue

[Imre Deak <imre.deak@intel.com>]

Running some basic igt tests on BXT A1 stepping uncovered a coherency
problem where a cached CPU mapping won't be updated by a GPU store via a
snooped mapping. While I opened an internal ticket to investigate this
further this patchset is an attempt to work around the problem until a
better solution is found or the problem is fixed in a later stepping.

The problem can be easily triggered with workloads where we submit
multiple small requests to the GPU. Here the CPU's view of seqno will
get eventually stale wrt. to the value stored by the GPU at the end of
the request and __wait_for_request will stall (and trigger the lost
interrupt/GPU reset mechanism). I could reproduce this with
igt/gem_store_dword_loop_render.

I also added a new igt/gem_store_dword_batches_loop for cached mappings
which shows the same problem in case of MI_STORE_MEMORY_IMM to a cached
buffer. The difference between this and the above case is that here the
buffer is mapped through PPGTT, while above the status page is mapped
through GGTT.

Imre Deak (2):
  drm/i915/bxt: work around HW coherency issue when accessing GPU seqno
  drm/i915/bxt: work around HW coherency issue for cached GEM mappings

 drivers/gpu/drm/i915/i915_gem.c         |  6 +++++-
 drivers/gpu/drm/i915/intel_lrc.c        | 17 +++++++++++++++++
 drivers/gpu/drm/i915/intel_ringbuffer.h |  7 +++++++
 3 files changed, 29 insertions(+), 1 deletion(-)

-- 
2.1.4

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