[PATCH 2/2] drm/i915/bxt: work around HW coherency issue for cached GEM mappings

Imre Deak
2015-06-08T16:49:22Z

Due to a coherency issue on BXT-A1 we can't guarantee a coherent view of
cached GPU mappings, so fall back to uncached mappings. Note that this
still won't fix cases where userspace expects a coherent view without
synchronizing (via a set domain call). It still makes sense to limit the
kernel's notion of the mapping to be uncached, for example for
relocations to work properly during execbuffer time. Also in case user
space does synchronize the buffer, this will still guarantee that we'll
do the proper clflushing for the buffer.

Testcast: igt/gem_store_dword_batches_loop/cached-mapping
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_gem.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index be35f04..212b51c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4062,7 +4062,11 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
level = I915_CACHE_NONE;
break;
case I915_CACHING_CACHED:
- level = I915_CACHE_LLC;
+ /*
+ * On BXT-A1 we can't guarantee a coherent view for cached
+ * mappings, so fall back to uncached mappings.
+ */
+ level = IS_BROXTON(dev) ? I915_CACHE_NONE : I915_CACHE_LLC;
break;
case I915_CACHING_DISPLAY:
level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
--
2.1.4