From: Imre Deak <imre.deak@intel.com>
To: Dave Gordon <david.s.gordon@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/i915/bxt: work around HW coherency issue when accessing GPU seqno
Date: Mon, 08 Jun 2015 20:14:44 +0300 [thread overview]
Message-ID: <1433783684.21280.12.camel@intel.com> (raw)
In-Reply-To: <5575CBF0.5090109@intel.com>
On ma, 2015-06-08 at 18:08 +0100, Dave Gordon wrote:
> On 08/06/15 17:28, Imre Deak wrote:
> > By running igt/store_dword_loop_render on BXT we can hit a coherency
> > problem where the seqno written at GPU command completion time is not
> > seen by the CPU. This results in __i915_wait_request seeing the stale
> > seqno and not completing the request (not considering the lost
> > interrupt/GPU reset mechanism). I also verified that this isn't a case
> > of a lost interrupt, or that the command didn't complete somehow: when
> > the coherency issue occured I read the seqno via an uncached GTT mapping
> > too. While the cached version of the seqno still showed the stale value
> > the one read via the uncached mapping was the correct one.
> >
> > Work around this issue by clflushing the corresponding CPU cacheline
> > following any store of the seqno and preceding any reading of it. When
> > reading it do this only when the caller expects a coherent view.
> >
> > Testcase: igt/store_dword_loop_render
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>
> Not necessarily a cure for this, but BSpec says of MI_STORE_DATA_IMM
> (and MI_STORE_DATA_INDEX):
>
> This command simply initiates the write operation with
> command execution proceeding normally. Although the write
> operation is guaranteed to complete "eventually", there is
> no mechanism to synchronize command execution with the
> completion (or even initiation) of these operations.
>
> So shouldn't we use MI_FLUSH_DW or PIPE_CONTROL to update the seqno in
> the HWSP instead?
I have tried to use PIPE_CONTROL instead of MI_STORE_DATA_IMM, but that
didn't solve this issue. With the new
igt/store_dword_batches_loop/cached-mapping you can also verify that
this isn't some ordering issue. By waiting enough after the command
completed the CPU's view is still stale. Reading it after a clflush
results in the correct value on the other hand.
--Imre
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next prev parent reply other threads:[~2015-06-08 17:14 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-08 16:28 [PATCH 0/2] drm/i915/bxt: work around HW coherency issue Imre Deak
2015-06-08 16:28 ` [PATCH 1/2] drm/i915/bxt: work around HW coherency issue when accessing GPU seqno Imre Deak
2015-06-08 17:08 ` Dave Gordon
2015-06-08 17:12 ` Chris Wilson
2015-06-08 17:34 ` Ville Syrjälä
2015-06-08 18:00 ` Chris Wilson
2015-06-08 18:40 ` Ville Syrjälä
2015-06-08 19:33 ` Dave Gordon
2015-06-10 10:59 ` Imre Deak
2015-06-10 15:10 ` Jesse Barnes
2015-06-10 15:26 ` Imre Deak
2015-06-10 15:33 ` Jesse Barnes
2015-06-10 15:55 ` Imre Deak
2015-06-10 15:52 ` Chris Wilson
2015-06-11 8:02 ` Dave Gordon
2015-06-11 8:20 ` Chris Wilson
2015-06-11 19:14 ` Imre Deak
2015-06-08 17:14 ` Imre Deak [this message]
2015-06-09 8:21 ` Jani Nikula
2015-06-10 14:07 ` Imre Deak
2015-06-10 14:21 ` Chris Wilson
2015-06-10 14:55 ` Imre Deak
2015-06-10 15:00 ` Ville Syrjälä
2015-06-10 15:16 ` Imre Deak
2015-06-10 15:35 ` Chris Wilson
2015-07-01 13:40 ` Mika Kuoppala
2015-07-01 13:53 ` Mika Kuoppala
2015-06-08 16:28 ` [PATCH 2/2] drm/i915/bxt: work around HW coherency issue for cached GEM mappings Imre Deak
2015-06-13 18:04 ` shuang.he
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