[PATCH v4 2/6] drm/i915/gen8: Re-order init pipe_control in lrc mode

Arun Siluvery
2015-06-16T19:25:31Z

Some of the WA applied using WA batch buffers perform writes to scratch page.
In the current flow WA are initialized before scratch obj is allocated.
This patch reorders intel_init_pipe_control() to have a valid scratch obj
before we initialize WA.

Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index cad274a..dcc3f2e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1608,7 +1608,8 @@ static int logical_render_ring_init(struct drm_device *dev)
ring->emit_bb_start = gen8_emit_bb_start;

ring->dev = dev;
- ret = logical_ring_init(dev, ring);
+
+ ret = intel_init_pipe_control(ring);
if (ret)
return ret;

@@ -1628,7 +1629,7 @@ static int logical_render_ring_init(struct drm_device *dev)
}
}

- ret = intel_init_pipe_control(ring);
+ ret = logical_ring_init(dev, ring);
if (ret) {
if (ring->wa_ctx.obj)
lrc_destroy_wa_ctx_obj(ring);
--
2.3.0