Re: [PATCH v4 4/6] drm/i915/gen8: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaround

Chris Wilson
2015-06-26T16:56:22Z

On Fri, Jun 26, 2015 at 05:45:08PM +0100, Dave Gordon wrote:
> On 16/06/15 21:38, Chris Wilson wrote:
> > On Tue, Jun 16, 2015 at 08:25:23PM +0100, Arun Siluvery wrote:
> >> + /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
> >> + if (IS_BROADWELL(ring->dev)) {
> >> + struct drm_i915_private *dev_priv = ring->dev->dev_private;
> >
> > dev_priv = to_i915(ring->dev);
> >
> >> +
> >> + cmd[index++] = MI_LOAD_REGISTER_IMM(1);
> >> + cmd[index++] = GEN8_L3SQCREG4;
> >> + cmd[index++] = I915_READ(GEN8_L3SQCREG4) |
> >> + GEN8_LQSC_FLUSH_COHERENT_LINES;
> >
> > Read the reg once, it is clearer that way.
> >
> >> +
> >> + cmd[index++] = GFX_OP_PIPE_CONTROL(6);
> >> + cmd[index++] = PIPE_CONTROL_CS_STALL |
> >> + PIPE_CONTROL_DC_FLUSH_ENABLE;
> >> + cmd[index++] = 0;
> >> + cmd[index++] = 0;
> >> + cmd[index++] = 0;
> >> + cmd[index++] = 0;
> >> +
> >> + cmd[index++] = MI_LOAD_REGISTER_IMM(1);
> >> + cmd[index++] = GEN8_L3SQCREG4;
> >> + cmd[index++] = I915_READ(GEN8_L3SQCREG4) &
> >> + ~GEN8_LQSC_FLUSH_COHERENT_LINES;
> > -Chris
>
> What Chris said. But also, is it even meaningful to read a h/w register
> now (when?) and use its value as the basis for future LRI instructions?
> How (and when) does this register get its initial value, and does it get
> changed at any other time? If the value we put in the register is a
> run-time constant, there's really no need to read it back even once.

True. To be generic, we need to do STORE_REG_MEM, LRI constant value,
then LOAD_REG_MEM. Hopefully, no userspace ever actually need to twiddle
that register and we can just load a constant value.
-Chris

--
Chris Wilson, Intel Open Source Technology Centre