[PATCH v4 5/6] drm/i915/gen8: Add WaClearSlmSpaceAtContextSwitch workaround

Arun Siluvery
2015-06-16T19:25:35Z

In Indirect context w/a batch buffer,
WaClearSlmSpaceAtContextSwitch

v2: s/PIPE_CONTROL_FLUSH_RO_CACHES/PIPE_CONTROL_FLUSH_L3 (Ville)

Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_lrc.c | 19 +++++++++++++++++++
2 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d14ad20..7637e64 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -410,6 +410,7 @@
#define DISPLAY_PLANE_A (0<<20)
#define DISPLAY_PLANE_B (1<<20)
#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
+#define PIPE_CONTROL_FLUSH_L3 (1<<27)
#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
#define PIPE_CONTROL_MMIO_WRITE (1<<23)
#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 92556b9..27e6692 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1085,6 +1085,8 @@ static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
uint32_t index;
struct page *page;
uint32_t *cmd;
+ u32 scratch_addr;
+ unsigned long flags = 0;

page = i915_gem_object_get_page(ring->wa_ctx.obj, 0);
cmd = kmap_atomic(page);
@@ -1117,6 +1119,23 @@ static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
~GEN8_LQSC_FLUSH_COHERENT_LINES;
}

+ /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
+ flags = PIPE_CONTROL_FLUSH_L3 |
+ PIPE_CONTROL_GLOBAL_GTT_IVB |
+ PIPE_CONTROL_CS_STALL |
+ PIPE_CONTROL_QW_WRITE;
+
+ /* Actual scratch location is at 128 bytes offset */
+ scratch_addr = ring->scratch.gtt_offset + 2*CACHELINE_BYTES;
+ scratch_addr |= PIPE_CONTROL_GLOBAL_GTT;
+
+ cmd[index++] = GFX_OP_PIPE_CONTROL(6);
+ cmd[index++] = flags;
+ cmd[index++] = scratch_addr;
+ cmd[index++] = 0;
+ cmd[index++] = 0;
+ cmd[index++] = 0;
+
/* padding */
while (((unsigned long) (cmd + index) % CACHELINE_BYTES) != 0)
cmd[index++] = MI_NOOP;
--
2.3.0