From: Imre Deak <imre.deak@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/i915: Add the ddi get cdclk code for BXT.
Date: Wed, 17 Jun 2015 17:43:24 +0300 [thread overview]
Message-ID: <1434552204.14700.28.camel@intel.com> (raw)
In-Reply-To: <20150615085909.GG5176@intel.com>
On ma, 2015-06-15 at 11:59 +0300, Ville Syrjälä wrote:
> On Wed, Jun 10, 2015 at 01:18:28PM -0700, Bob Paauwe wrote:
> > The registers and process differ from other platforms.
> >
> > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 27 +++++++++++++++++++++++++++
> > 1 file changed, 27 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index c38c297..41464a5 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -6687,6 +6687,30 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
> > return 24000;
> > }
> >
> > +static int broxton_get_display_clock_speed(struct drm_device *dev)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > + uint32_t cdctl = I915_READ(CDCLK_CTL);
> > + uint32_t pll_freq = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
> > +
>
> You should return 19.2MHz if the DE PLL isn't enabled.
Agreed with Ville, Bob could you resend the patch with this fixed?
> > + switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
> > + case BXT_CDCLK_CD2X_DIV_SEL_1:
> > + if (pll_freq == BXT_DE_PLL_RATIO(60)) /* PLL freq = 1152MHz */
> > + return 576000;
> > + else /* PLL freq = 1248MHz */
> > + return 624000;
> > + case BXT_CDCLK_CD2X_DIV_SEL_1_5:
> > + return 384000;
> > + case BXT_CDCLK_CD2X_DIV_SEL_2:
> > + return 288000;
> > + case BXT_CDCLK_CD2X_DIV_SEL_4:
> > + return 144000;
> > + }
> > +
> > + /* error case, assume higer PLL freq. */
> > + return 624000;
> > +}
> > +
> > static int broadwell_get_display_clock_speed(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -14649,6 +14673,9 @@ static void intel_init_display(struct drm_device *dev)
> > if (IS_SKYLAKE(dev))
> > dev_priv->display.get_display_clock_speed =
> > skylake_get_display_clock_speed;
> > + else if (IS_BROXTON(dev))
> > + dev_priv->display.get_display_clock_speed =
> > + broxton_get_display_clock_speed;
> > else if (IS_BROADWELL(dev))
> > dev_priv->display.get_display_clock_speed =
> > broadwell_get_display_clock_speed;
> > --
> > 2.1.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
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next prev parent reply other threads:[~2015-06-17 14:43 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-10 20:18 [PATCH] drm/i915: Add the ddi get cdclk code for BXT Bob Paauwe
2015-06-14 11:45 ` shuang.he
2015-06-15 8:59 ` Ville Syrjälä
2015-06-17 14:43 ` Imre Deak [this message]
2015-06-18 16:38 ` [PATCH] drm/i915: Add the ddi get cdclk code for BXT (v2) Matt Roper
2015-06-22 13:26 ` Ville Syrjälä
2015-06-23 21:14 ` [PATCH] drm/i915: Add the ddi get cdclk code for BXT (v3) Bob Paauwe
2015-06-24 12:49 ` Ville Syrjälä
2015-06-24 13:11 ` Daniel Vetter
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