From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: [PATCH v3] drm/i915: fix backlight after resume on 855gm Date: Fri, 26 Jun 2015 14:18:56 +0300 Message-ID: <1435317536-15362-1-git-send-email-jani.nikula@intel.com> References: <20150626110330.GB7632@nuc-i3427.alporthouse.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <20150626110330.GB7632@nuc-i3427.alporthouse.com> Sender: stable-owner@vger.kernel.org To: Chris Wilson , Jani Nikula Cc: intel-gfx@lists.freedesktop.org, ville.syrjala@linux.intel.com, stable@vger.kernel.org, phg@phi-gamma.net List-Id: intel-gfx@lists.freedesktop.org Some 855gm models (at least ThinkPad X40) regressed because of commit b0cd324faed23d10d66ba6ade66579c681feef6f Author: Jani Nikula Date: Wed Nov 12 16:25:43 2014 +0200 drm/i915: don't save/restore backlight hist ctl registers which tried to make our driver more robust by not blindly saving and restoring registers, but it failed to take into account commit 0eb96d6ed38430b72897adde58f5477a6b71757a Author: Jesse Barnes Date: Wed Oct 14 12:33:41 2009 -0700 drm/i915: save/restore BLC histogram control reg across suspend/res= ume =46ix the regression by enabling hist ctl on gen2. v2: Improved the comment. v3: Improved the comment, again. Reported-and-tested-by: Philipp Gesang References: http://mid.gmane.org/20150623222648.GD12335@acheron =46ixes: b0cd324faed2 ("drm/i915: don't save/restore backlight hist ctl= registers") Cc: Ville Syrj=C3=A4l=C3=A4 Cc: stable@vger.kernel.org Acked-by: Chris Wilson Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_panel.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i91= 5_reg.h index fa9ccb87eb66..bf7c08b94088 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3507,6 +3507,7 @@ enum skl_disp_power_wells { #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ =20 #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260) +#define BLM_HISTOGRAM_ENABLE (1 << 31) =20 /* New registers for PCH-split platforms. Safe where new bits show up,= the * register layout machtes with gen4 BLC_PWM_CTL[12]. */ diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/= intel_panel.c index 7d83527f95f7..55aad2322e10 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -907,6 +907,14 @@ static void i9xx_enable_backlight(struct intel_con= nector *connector) =20 /* XXX: combine this into above write? */ intel_panel_actually_set_backlight(connector, panel->backlight.level)= ; + + /* + * Needed to enable backlight on some 855gm models. BLC_HIST_CTL is + * 855gm only, but checking for gen2 is safe, as 855gm is the only ge= n2 + * that has backlight. + */ + if (IS_GEN2(dev)) + I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE); } =20 static void i965_enable_backlight(struct intel_connector *connector) --=20 2.1.4