From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mika Kahola Subject: [PATCH 4/9] drm/i915: Check pixel clock when setting mode for DVO Date: Fri, 3 Jul 2015 14:35:52 +0300 Message-ID: <1435923357-3821-5-git-send-email-mika.kahola@intel.com> References: <1435923357-3821-1-git-send-email-mika.kahola@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 34A6A4A058 for ; Fri, 3 Jul 2015 04:34:12 -0700 (PDT) In-Reply-To: <1435923357-3821-1-git-send-email-mika.kahola@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org SXQgaXMgcG9zc2libGUgdGhlIHdlIHJlcXVlc3QgdG8gaGF2ZSBhIG1vZGUgdGhhdCBoYXMKaGln aGVyIHBpeGVsIGNsb2NrIHRoYW4gb3VyIEhXIGNhbiBzdXBwb3J0LiBUaGlzIHBhdGNoCmNoZWNr cyBpZiByZXF1ZXN0ZWQgcGl4ZWwgY2xvY2sgaXMgbG93ZXIgdGhhbiB0aGUgb25lCnN1cHBvcnRl ZCBieSB0aGUgSFcuIFRoZSByZXF1ZXN0ZWQgbW9kZSBpcyBkaXNjYXJkZWQKaWYgd2UgY2Fubm90 IHN1cHBvcnQgdGhlIHJlcXVlc3RlZCBwaXhlbCBjbG9jay4KClRoaXMgcGF0Y2ggYXBwbGllcyB0 byBEVk8uCgpTaWduZWQtb2ZmLWJ5OiBNaWthIEthaG9sYSA8bWlrYS5rYWhvbGFAaW50ZWwuY29t PgotLS0KIGRyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2R2by5jIHwgMjEgKysrKysrKysrKysr KysrKysrKystCiAxIGZpbGUgY2hhbmdlZCwgMjAgaW5zZXJ0aW9ucygrKSwgMSBkZWxldGlvbigt KQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2R2by5jIGIvZHJpdmVy cy9ncHUvZHJtL2k5MTUvaW50ZWxfZHZvLmMKaW5kZXggZWNlNWJkNy4uODJjYmNlYSAxMDA2NDQK LS0tIGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZHZvLmMKKysrIGIvZHJpdmVycy9ncHUv ZHJtL2k5MTUvaW50ZWxfZHZvLmMKQEAgLTI0MCwxNiArMjQwLDM1IEBAIHN0YXRpYyB2b2lkIGlu dGVsX2R2b19kcG1zKHN0cnVjdCBkcm1fY29ubmVjdG9yICpjb25uZWN0b3IsIGludCBtb2RlKQog CWludGVsX21vZGVzZXRfY2hlY2tfc3RhdGUoY29ubmVjdG9yLT5kZXYpOwogfQogCitzdGF0aWMg aW50CitpbnRlbF9kdm9fbWF4X3BpeGNsayhzdHJ1Y3QgaW50ZWxfZHZvICppbnRlbF9kdm8pCit7 CisJc3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmRldl9wcml2ID0gaW50ZWxfZHZvLT5kZXYuZGV2 X3ByaXY7CisJc3RydWN0IGludGVsX2NydGMgKmludGVsX2NydGMgPSB0b19pbnRlbF9jcnRjKGlu dGVsX2R2by0+YmFzZS5iYXNlLmNydGMpOworCisJaWYgKElTX0NIRVJSWVZJRVcoZGV2X3ByaXYp KQorCQlyZXR1cm4gIERJVl9ST1VORF9VUChkZXZfcHJpdi0+bWF4X2NkY2xrX2ZyZXEgKiAxMDAs IDk1KTsKKwllbHNlIGlmIChJU19WQUxMRVlWSUVXKGRldl9wcml2KSkKKwkJcmV0dXJuICBESVZf Uk9VTkRfVVAoZGV2X3ByaXYtPm1heF9jZGNsa19mcmVxICogMTAwLCA5MCk7CisJZWxzZSBpZiAo SVNfQlJPQURXRUxMKGRldl9wcml2KSAmJiBpbnRlbF9jcnRjLT5jb25maWctPmlwc19lbmFibGVk KQorCQlyZXR1cm4gIERJVl9ST1VORF9VUChkZXZfcHJpdi0+bWF4X2NkY2xrX2ZyZXEgKiAxMDAs IDk1KTsKKwllbHNlCisJCXJldHVybiBkZXZfcHJpdi0+bWF4X2NkY2xrX2ZyZXE7Cit9CisKIHN0 YXRpYyBlbnVtIGRybV9tb2RlX3N0YXR1cwogaW50ZWxfZHZvX21vZGVfdmFsaWQoc3RydWN0IGRy bV9jb25uZWN0b3IgKmNvbm5lY3RvciwKIAkJICAgICBzdHJ1Y3QgZHJtX2Rpc3BsYXlfbW9kZSAq bW9kZSkKIHsKIAlzdHJ1Y3QgaW50ZWxfZHZvICppbnRlbF9kdm8gPSBpbnRlbF9hdHRhY2hlZF9k dm8oY29ubmVjdG9yKTsKKwlpbnQgbWF4X3BpeGNsayA9IGludGVsX2R2b19tYXhfcGl4Y2xrKGlu dGVsX2R2byk7CiAKIAlpZiAobW9kZS0+ZmxhZ3MgJiBEUk1fTU9ERV9GTEFHX0RCTFNDQU4pCiAJ CXJldHVybiBNT0RFX05PX0RCTEVTQ0FOOwogCi0JLyogWFhYOiBWYWxpZGF0ZSBjbG9jayByYW5n ZSAqLworCS8qIFZhbGlkYXRlIGNsb2NrIHJhbmdlICovCisJaWYgKG1vZGUtPmNsb2NrID4gbWF4 X3BpeGNsaykKKwkJcmV0dXJuIE1PREVfUEFORUw7CiAKIAlpZiAoaW50ZWxfZHZvLT5wYW5lbF9m aXhlZF9tb2RlKSB7CiAJCWlmIChtb2RlLT5oZGlzcGxheSA+IGludGVsX2R2by0+cGFuZWxfZml4 ZWRfbW9kZS0+aGRpc3BsYXkpCi0tIAoxLjkuMQoKX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlz dHMuZnJlZWRlc2t0b3Aub3JnCmh0dHA6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9s aXN0aW5mby9pbnRlbC1nZngK