Re: [PATCH v4 03/18] drm/i915/gen8: Add PML4 structure

Chris Wilson
2015-07-13T20:02:36Z

On Mon, Jul 13, 2015 at 03:41:38PM +0100, Michel Thierry wrote:
> On 7/11/2015 9:02 PM, Chris Wilson wrote:
> >On Tue, Jul 07, 2015 at 04:14:48PM +0100, Michel Thierry wrote:
> >>Introduces the Page Map Level 4 (PML4), ie. the new top level structure
> >>of the page tables.
> >>
> >>To facilitate testing, 48b mode will be available on Broadwell and
> >>GEN9+, when i915.enable_ppgtt = 3.
> >>
> >>Cc: Akash Goel <akash.goel@intel.com>
> >>Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> >>---
> >> drivers/gpu/drm/i915/i915_drv.h | 7 ++++++-
> >> drivers/gpu/drm/i915/i915_gem_gtt.c | 40 ++++++++++++++++++++++++-------------
> >> drivers/gpu/drm/i915/i915_gem_gtt.h | 35 ++++++++++++++++++++++++--------
> >> 3 files changed, 59 insertions(+), 23 deletions(-)
> >>
> >>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> >>index 464b28d..de3a5d1 100644
> >>--- a/drivers/gpu/drm/i915/i915_drv.h
> >>+++ b/drivers/gpu/drm/i915/i915_drv.h
> >>@@ -2497,7 +2497,12 @@ struct drm_i915_cmd_table {
> >> #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
> >> #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
> >> #define USES_PPGTT(dev) (i915.enable_ppgtt)
> >>-#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
> >>+#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
> >>+#ifdef CONFIG_X86_64
> >>+# define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
> >>+#else
> >>+# define USES_FULL_48BIT_PPGTT(dev) false
> >>+#endif
> >
> >This requires an explanation.
> >-Chris
> >
> Actually, this is no longer necessary after Mika's changes:
>
> commit c44ef60e437019b8ca1dab8b4d2e8761fd4ce1e9
> Author: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Date: Thu Jun 25 18:35:05 2015 +0300
>
> drm/i915/gtt: Allow >= 4GB sizes for vm.

I thought as much, and would have appreciated a
/* FIXME not all GTT handling code is 32/64bit safe yet */
just to confirm that the problem was our code and not a hardware
restriction.
-Chris

--
Chris Wilson, Intel Open Source Technology Centre