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From: Michel Thierry <michel.thierry@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: akash.goel@intel.com
Subject: [PATCH v5 15/19] drm/i915: batch_obj vm offset must be u64
Date: Thu, 16 Jul 2015 10:33:27 +0100	[thread overview]
Message-ID: <1437039211-2507-16-git-send-email-michel.thierry@intel.com> (raw)
In-Reply-To: <1437039211-2507-1-git-send-email-michel.thierry@intel.com>

Otherwise it can overflow in 48-bit mode, and cause an incorrect
exec_start.

Before commit 5f19e2bffa63a91cd4ac1adcec648e14a44277ce ("drm/i915: Merged
the many do_execbuf() parameters into a structure"), it was already an u64.

Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 649408a..1dbbbf0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1674,7 +1674,7 @@ struct i915_execbuffer_params {
 	struct drm_file                 *file;
 	uint32_t                        dispatch_flags;
 	uint32_t                        args_batch_start_offset;
-	uint32_t                        batch_obj_vm_offset;
+	uint64_t                        batch_obj_vm_offset;
 	struct intel_engine_cs          *ring;
 	struct drm_i915_gem_object      *batch_obj;
 	struct intel_context            *ctx;
-- 
2.4.5

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  parent reply	other threads:[~2015-07-16  9:33 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-16  9:33 [PATCH v5 00/19] 48-bit PPGTT Michel Thierry
2015-07-16  9:33 ` [PATCH v5 01/19] drm/i915: Remove unnecessary gen8_clamp_pd Michel Thierry
2015-07-16  9:33 ` [PATCH v5 02/19] drm/i915/gen8: Make pdp allocation more dynamic Michel Thierry
2015-07-16  9:33 ` [PATCH v5 03/19] drm/i915/gen8: Abstract PDP usage Michel Thierry
2015-07-16  9:33 ` [PATCH v5 04/19] drm/i915/gen8: Add dynamic page trace events Michel Thierry
2015-07-16  9:33 ` [PATCH v5 05/19] drm/i915/gen8: Add PML4 structure Michel Thierry
2015-07-16  9:33 ` [PATCH v5 06/19] drm/i915/gen8: implement alloc/free for 4lvl Michel Thierry
2015-07-29 14:34   ` Michel Thierry
2015-07-16  9:33 ` [PATCH v5 07/19] drm/i915/gen8: Add 4 level switching infrastructure and lrc support Michel Thierry
2015-07-29 14:34   ` Michel Thierry
2015-07-16  9:33 ` [PATCH v5 08/19] drm/i915/gen8: Generalize PTE writing for GEN8 PPGTT Michel Thierry
2015-07-29 14:35   ` Michel Thierry
2015-07-16  9:33 ` [PATCH v5 09/19] drm/i915/gen8: Pass sg_iter through pte inserts Michel Thierry
2015-07-16  9:33 ` [PATCH v5 10/19] drm/i915/gen8: Add 4 level support in insert_entries and clear_range Michel Thierry
2015-07-16  9:33 ` [PATCH v5 11/19] drm/i915/gen8: Initialize PDPs Michel Thierry
2015-07-29 14:35   ` Michel Thierry
2015-07-16  9:33 ` [PATCH v5 12/19] drm/i915: Expand error state's address width to 64b Michel Thierry
2015-07-16  9:33 ` [PATCH v5 13/19] drm/i915/gen8: Add ppgtt info and debug_dump Michel Thierry
2015-07-16  9:33 ` [PATCH v5 14/19] drm/i915: object size needs to be u64 Michel Thierry
2015-07-16  9:33 ` Michel Thierry [this message]
2015-07-16  9:33 ` [PATCH v5 16/19] drm/i915/userptr: Kill user_size limit check Michel Thierry
2015-07-16  9:33 ` [PATCH v5 17/19] drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset Michel Thierry
2015-07-27 14:34   ` Goel, Akash
2015-07-27 14:46     ` Chris Wilson
2015-07-27 14:53       ` Michel Thierry
2015-07-27 21:11   ` Chris Wilson
2015-07-28 11:12     ` Michel Thierry
2015-07-28 14:43       ` Chris Wilson
2015-07-29 11:05         ` Michel Thierry
2015-07-29 11:17           ` Chris Wilson
2015-07-16  9:33 ` [PATCH v5 18/19] drm/i915/gen8: Flip the 48b switch Michel Thierry
2015-07-16  9:33 ` [PATCH v5 19/19] drm/i915: Save some page table setup on repeated binds Michel Thierry
2015-07-28 12:18 ` [PATCH v5 00/19] 48-bit PPGTT Chris Wilson

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