[MIPI SEQ V3 PARSING PATCH 0/9] Patches to support the version 3 of MIPI sequence in VBT.

[MIPI SEQ V3 PARSING PATCH 0/9] Patches to support the version 3 of MIPI sequence in VBT.

[Deepak M]

Currently in our kernel we ioremap 8KB of memory for the
opregion and it holds a maximum of 6KB sized RAW vbt data.

As per the latest opregion spec when the VBT size exceeds
6KB it cant be placed in the mailbox4 of the opregion, so
the physical address of the buffer where the Raw VBT is
stored will be mentioned in the mailbox3 with the VBT size
in the opregion version 2 and above.
A non-zero value here is an indication to driver that a
valid Raw VBT is stored here and driver should not refer
to mailbox4 for getting VBT. This is implemented in one
of the patches in this series.

link for the opregion spec : https://securewiki.ith.intel.com/pages/viewpage.action?pageId=48147378
(spec is under intel firewall)

In the version 3 of the MIPI sequence block, the size
field is 4 bytes so that it can support block size of
more than 64KB, but the vbt size field in the bdb header is only
2 bytes. Based on the below points this issue can be handled.
1. When the VBT is not present in the mailbox4 then VBT size
needs to be read from the mailbox3 and this VBT size field
is of 4 bytes which implies that it can be more than 64KB also.
2. If the VBT size is more than 64KB then the VBT size field
in the bdb header cant be relied. So its better to consider
the vbt size from the mailbox3 when the VBT is not present in
mailbox4.

Other patches implements the parsing of the new sequence type
which are added in the block 53 and adding new wrapper functions
for the struct drm_panel_funcs.

Deepak M (4):
  drm/i915: Parsing VBT if size of VBT exceeds 6KB
  drm/i915: Using the approprite vbt size if vbt is not in mailbox4 of
    opregion
  drm/i915: Added the generic gpio sequence support and gpio table
  drm: Add few more wrapper functions for drm panel

Gaurav K Singh (1):
  drm/i915: Add functions to execute the new sequences from VBT

Uma Shankar (1):
  BXT GPIO support for backlight and panel control

Yogesh Mohan Marimuthu (1):
  drm/i915: GPIO for CHT generic MIPI

vkorjani (2):
  drm/i915: Adding the parsing logic for the i2c element
  drm/i915: Added support the v3 mipi sequence block

 drivers/gpu/drm/i915/i915_drv.h            |   10 +-
 drivers/gpu/drm/i915/i915_reg.h            |   28 ++
 drivers/gpu/drm/i915/intel_bios.c          |  181 +++++++---
 drivers/gpu/drm/i915/intel_bios.h          |    9 +
 drivers/gpu/drm/i915/intel_dsi.h           |  355 +++++++++++++++++++
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |  513 ++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_opregion.c      |   42 ++-
 drivers/gpu/drm/i915/intel_sideband.c      |    9 +-
 include/drm/drm_panel.h                    |   47 +++
 9 files changed, 1119 insertions(+), 75 deletions(-)

-- 
1.7.9.5

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[MIPI SEQ PARSING v1 PATCH 1/9] drm/i915: Adding the parsing logic for the i2c element

[Deepak M]

From: vkorjani <vikas.korjani@intel.com>

New sequence element for i2c is been added in the
mipi sequence block of the VBT. This patch parses
and executes the i2c sequence.

Signed-off-by: vkorjani <vikas.korjani@intel.com>
Signed-off-by: Deepak M <m.deepak@intel.com>
---
 drivers/gpu/drm/i915/intel_bios.c          |    6 +++
 drivers/gpu/drm/i915/intel_bios.h          |    1 +
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   59 ++++++++++++++++++++++++++++
 3 files changed, 66 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 2ff9eb0..2583587 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -714,6 +714,12 @@ static u8 *goto_next_sequence(u8 *data, int *size)
 
 			data += 3;
 			break;
+		case MIPI_SEQ_ELEM_I2C:
+			/* skip by this element payload size */
+			data += 7;
+			len = *data;
+			data += len + 1;
+			break;
 		default:
 			DRM_ERROR("Unknown element\n");
 			return NULL;
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index af0b476..1703a83 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -942,6 +942,7 @@ enum mipi_seq_element {
 	MIPI_SEQ_ELEM_SEND_PKT,
 	MIPI_SEQ_ELEM_DELAY,
 	MIPI_SEQ_ELEM_GPIO,
+	MIPI_SEQ_ELEM_I2C,
 	MIPI_SEQ_ELEM_STATUS,
 	MIPI_SEQ_ELEM_MAX
 };
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index a5e99ac..e061a42 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -31,6 +31,7 @@
 #include <drm/drm_panel.h>
 #include <linux/slab.h>
 #include <video/mipi_display.h>
+#include <linux/i2c.h>
 #include <asm/intel-mid.h>
 #include <video/mipi_display.h>
 #include "i915_drv.h"
@@ -104,6 +105,63 @@ static struct gpio_table gtable[] = {
 	{ GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
 };
 
+static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
+{
+	struct i2c_adapter *adapter;
+	int ret;
+	u8 reg_offset, payload_size, retries = 5;
+	struct i2c_msg msg;
+	u8 *transmit_buffer = NULL;
+	u8 flag = *data++;
+	u8 index = *data++;
+	u8 bus_number = *data++;
+	u16 slave_add = *(u16 *)(data);
+
+	data = data + 2;
+	reg_offset = *data++;
+	payload_size = *data++;
+
+	adapter = i2c_get_adapter(bus_number);
+
+	if (!adapter) {
+		DRM_ERROR("i2c_get_adapter(%u) failed, index:%u flag: %u\n",
+				(bus_number + 1), index, flag);
+		goto out;
+	}
+
+	transmit_buffer = kmalloc(1 + payload_size, GFP_TEMPORARY);
+
+	if (!transmit_buffer)
+		goto out;
+
+	transmit_buffer[0] = reg_offset;
+	memcpy(&transmit_buffer[1], data, (size_t)payload_size);
+
+	msg.addr   = slave_add;
+	msg.flags  = 0;
+	msg.len    = 2;
+	msg.buf    = &transmit_buffer[0];
+
+	do {
+		ret =  i2c_transfer(adapter, &msg, 1);
+		if (ret == -EAGAIN)
+			usleep_range(1000, 2500);
+		else if (ret != 1) {
+			DRM_ERROR("i2c transfer failed %d\n", ret);
+			break;
+		}
+	} while (retries--);
+
+	if (retries == 0)
+		DRM_ERROR("i2c transfer failed");
+
+out:
+	kfree(transmit_buffer);
+
+	data = data + payload_size;
+	return data;
+}
+
 static inline enum port intel_dsi_seq_port_to_port(u8 port)
 {
 	return port ? PORT_C : PORT_A;
@@ -236,6 +294,7 @@ static const fn_mipi_elem_exec exec_elem[] = {
 	mipi_exec_send_packet,
 	mipi_exec_delay,
 	mipi_exec_gpio,
+	mipi_exec_i2c,
 	NULL, /* status read; later */
 };
 
-- 
1.7.9.5

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[MIPI SEQ PARSING v1 PATCH 2/9] drm/i915: Parsing VBT if size of VBT exceeds 6KB

[Deepak M]

Currently the iomap for VBT works only if the size of the
VBT is less than 6KB, but if the size of the VBT exceeds
6KB than the physical address and the size of the VBT to
be iomapped is specified in the mailbox3 and is iomapped
accordingly.

Signed-off-by: Deepak M <m.deepak@intel.com>
---
 drivers/gpu/drm/i915/intel_bios.c     |   13 +++++++----
 drivers/gpu/drm/i915/intel_opregion.c |   39 ++++++++++++++++++++++++++++++---
 2 files changed, 45 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 2583587..1b9164e 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1219,6 +1219,7 @@ intel_parse_bios(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct pci_dev *pdev = dev->pdev;
 	const struct bdb_header *bdb = NULL;
+	const struct vbt_header *vbt = NULL;
 	u8 __iomem *bios = NULL;
 
 	if (HAS_PCH_NOP(dev))
@@ -1226,10 +1227,14 @@ intel_parse_bios(struct drm_device *dev)
 
 	init_vbt_defaults(dev_priv);
 
-	/* XXX Should this validation be moved to intel_opregion.c? */
-	if (!dmi_check_system(intel_no_opregion_vbt) && dev_priv->opregion.vbt)
-		bdb = validate_vbt(dev_priv->opregion.header, OPREGION_SIZE,
-				   dev_priv->opregion.vbt, "OpRegion");
+	if (!dmi_check_system(intel_no_opregion_vbt) &&
+			dev_priv->opregion.vbt) {
+		vbt = (struct vbt_header *)dev_priv->opregion.vbt;
+		bdb = (struct bdb_header *)(dev_priv->opregion.vbt +
+				vbt->bdb_offset);
+		DRM_DEBUG_KMS("Using VBT from Opregion: %20s\n",
+				vbt->signature);
+	}
 
 	if (bdb == NULL) {
 		size_t size;
diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
index 71e87ab..1372e39 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -50,6 +50,7 @@
 #define OPREGION_VBT_OFFSET    0x400
 
 #define OPREGION_SIGNATURE "IntelGraphicsMem"
+#define VBT_SIGNATURE	"$VBT"
 #define MBOX_ACPI      (1<<0)
 #define MBOX_SWSCI     (1<<1)
 #define MBOX_ASLE      (1<<2)
@@ -113,7 +114,12 @@ struct opregion_asle {
 	u32 pcft;       /* power conservation features */
 	u32 srot;       /* supported rotation angles */
 	u32 iuer;       /* IUER events */
-	u8 rsvd[86];
+	u64 fdss;	/* DSS Buffer address allocated for IFFS feature */
+	u32 fdsp;	/* Size of DSS Buffer */
+	u32 stat;	/* State Indicator */
+	u64 rvda;	/* Physical address of raw vbt data */
+	u32 rvds;	/* Size of raw vbt data */
+	u8 rsvd[58];
 } __packed;
 
 /* Driver readiness indicator */
@@ -858,8 +864,10 @@ int intel_opregion_setup(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_opregion *opregion = &dev_priv->opregion;
 	void __iomem *base;
+	void __iomem *vbt_base;
 	u32 asls, mboxes;
 	char buf[sizeof(OPREGION_SIGNATURE)];
+	char vbt_sig_buf[sizeof(VBT_SIGNATURE)];
 	int err = 0;
 
 	pci_read_config_dword(dev->pdev, PCI_ASLS, &asls);
@@ -873,7 +881,7 @@ int intel_opregion_setup(struct drm_device *dev)
 	INIT_WORK(&opregion->asle_work, asle_work);
 #endif
 
-	base = acpi_os_ioremap(asls, OPREGION_SIZE);
+	base = acpi_os_ioremap(asls, OPREGION_VBT_OFFSET);
 	if (!base)
 		return -ENOMEM;
 
@@ -884,8 +892,31 @@ int intel_opregion_setup(struct drm_device *dev)
 		err = -EINVAL;
 		goto err_out;
 	}
+
 	opregion->header = base;
-	opregion->vbt = base + OPREGION_VBT_OFFSET;
+	opregion->asle = base + OPREGION_ASLE_OFFSET;
+
+	if (opregion->header->opregion_ver >= 2) {
+		if (opregion->asle->rvda)
+			vbt_base = acpi_os_ioremap(opregion->asle->rvda,
+						opregion->asle->rvds);
+		else
+			vbt_base = acpi_os_ioremap(asls + OPREGION_VBT_OFFSET,
+					OPREGION_SIZE - OPREGION_VBT_OFFSET);
+	} else
+		vbt_base = acpi_os_ioremap(asls + OPREGION_VBT_OFFSET,
+					OPREGION_SIZE - OPREGION_VBT_OFFSET);
+
+
+	memcpy_fromio(vbt_sig_buf, vbt_base, sizeof(vbt_sig_buf));
+
+	if (memcmp(vbt_sig_buf, VBT_SIGNATURE, 4)) {
+		DRM_ERROR("VBT signature mismatch\n");
+		err = -EINVAL;
+		goto err_vbt;
+	}
+
+	opregion->vbt = vbt_base;
 
 	opregion->lid_state = base + ACPI_CLID;
 
@@ -909,6 +940,8 @@ int intel_opregion_setup(struct drm_device *dev)
 
 	return 0;
 
+err_vbt:
+	iounmap(vbt_base);
 err_out:
 	iounmap(base);
 	return err;
-- 
1.7.9.5

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[MIPI SEQ PARSING v1 PATCH 3/9] drm/i915: Using the approprite vbt size if vbt is not in mailbox4 of opregion

[Deepak M]

Currently the field in bdb header which indicates the VBT size
is of 2 bytes, but there are some cases where VBT size exceeds
64KB in which case this field may not contain the correct VBT size.
So its better to get the VBT size from the mailbox3 if
VBT is not present in the mailbox4 of opregion.

Signed-off-by: Deepak M <m.deepak@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |    5 ++++
 drivers/gpu/drm/i915/intel_bios.c     |   43 +++++++++++++++++++--------------
 drivers/gpu/drm/i915/intel_opregion.c |    7 ++++--
 3 files changed, 35 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1dbd957..b38f52ee 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1740,6 +1740,11 @@ struct drm_i915_private {
 	u32 pm_rps_events;
 	u32 pipestat_irq_mask[I915_MAX_PIPES];
 
+	bool vbt_in_mailbox4;
+
+	/* value is true when VBT is present in mailbox4 */
+	u32 vbt_size;
+
 	struct i915_hotplug hotplug;
 	struct i915_fbc fbc;
 	struct i915_drrs drrs;
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 1b9164e..5e0ff22 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -37,17 +37,22 @@
 static int panel_type;
 
 static const void *
-find_section(const void *_bdb, int section_id)
+find_section(struct drm_i915_private *dev_priv,
+		const void *_bdb, int section_id)
 {
 	const struct bdb_header *bdb = _bdb;
 	const u8 *base = _bdb;
 	int index = 0;
-	u16 total, current_size;
+	u32 total, current_size;
 	u8 current_id;
 
 	/* skip to first section */
 	index += bdb->header_size;
-	total = bdb->bdb_size;
+
+	if (dev_priv->vbt_in_mailbox4)
+		total = bdb->bdb_size;
+	else
+		total = dev_priv->vbt_size;
 
 	/* walk the sections looking for section_id */
 	while (index + 3 < total) {
@@ -179,7 +184,7 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
 	struct drm_display_mode *panel_fixed_mode;
 	int drrs_mode;
 
-	lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
+	lvds_options = find_section(dev_priv, bdb, BDB_LVDS_OPTIONS);
 	if (!lvds_options)
 		return;
 
@@ -211,11 +216,12 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
 		break;
 	}
 
-	lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
+	lvds_lfp_data = find_section(dev_priv, bdb, BDB_LVDS_LFP_DATA);
 	if (!lvds_lfp_data)
 		return;
 
-	lvds_lfp_data_ptrs = find_section(bdb, BDB_LVDS_LFP_DATA_PTRS);
+	lvds_lfp_data_ptrs = find_section(dev_priv, bdb,
+					BDB_LVDS_LFP_DATA_PTRS);
 	if (!lvds_lfp_data_ptrs)
 		return;
 
@@ -257,7 +263,7 @@ parse_lfp_backlight(struct drm_i915_private *dev_priv,
 	const struct bdb_lfp_backlight_data *backlight_data;
 	const struct bdb_lfp_backlight_data_entry *entry;
 
-	backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT);
+	backlight_data = find_section(dev_priv, bdb, BDB_LVDS_BACKLIGHT);
 	if (!backlight_data)
 		return;
 
@@ -305,14 +311,15 @@ parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
 	if (index == -1) {
 		const struct bdb_sdvo_lvds_options *sdvo_lvds_options;
 
-		sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS);
+		sdvo_lvds_options = find_section(dev_priv, bdb,
+						BDB_SDVO_LVDS_OPTIONS);
 		if (!sdvo_lvds_options)
 			return;
 
 		index = sdvo_lvds_options->panel_type;
 	}
 
-	dvo_timing = find_section(bdb, BDB_SDVO_PANEL_DTDS);
+	dvo_timing = find_section(dev_priv, bdb, BDB_SDVO_PANEL_DTDS);
 	if (!dvo_timing)
 		return;
 
@@ -349,7 +356,7 @@ parse_general_features(struct drm_i915_private *dev_priv,
 	struct drm_device *dev = dev_priv->dev;
 	const struct bdb_general_features *general;
 
-	general = find_section(bdb, BDB_GENERAL_FEATURES);
+	general = find_section(dev_priv, bdb, BDB_GENERAL_FEATURES);
 	if (general) {
 		dev_priv->vbt.int_tv_support = general->int_tv_support;
 		dev_priv->vbt.int_crt_support = general->int_crt_support;
@@ -374,7 +381,7 @@ parse_general_definitions(struct drm_i915_private *dev_priv,
 {
 	const struct bdb_general_definitions *general;
 
-	general = find_section(bdb, BDB_GENERAL_DEFINITIONS);
+	general = find_section(dev_priv, bdb, BDB_GENERAL_DEFINITIONS);
 	if (general) {
 		u16 block_size = get_blocksize(general);
 		if (block_size >= sizeof(*general)) {
@@ -405,7 +412,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
 	int i, child_device_num, count;
 	u16	block_size;
 
-	p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
+	p_defs = find_section(dev_priv, bdb, BDB_GENERAL_DEFINITIONS);
 	if (!p_defs) {
 		DRM_DEBUG_KMS("No general definition block is found, unable to construct sdvo mapping.\n");
 		return;
@@ -491,7 +498,7 @@ parse_driver_features(struct drm_i915_private *dev_priv,
 {
 	const struct bdb_driver_features *driver;
 
-	driver = find_section(bdb, BDB_DRIVER_FEATURES);
+	driver = find_section(dev_priv, bdb, BDB_DRIVER_FEATURES);
 	if (!driver)
 		return;
 
@@ -519,7 +526,7 @@ parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 	const struct edp_power_seq *edp_pps;
 	const struct edp_link_params *edp_link_params;
 
-	edp = find_section(bdb, BDB_EDP);
+	edp = find_section(dev_priv, bdb, BDB_EDP);
 	if (!edp) {
 		if (dev_priv->vbt.edp_support)
 			DRM_DEBUG_KMS("No eDP BDB found but eDP panel supported.\n");
@@ -630,7 +637,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 	const struct bdb_psr *psr;
 	const struct psr_table *psr_table;
 
-	psr = find_section(bdb, BDB_PSR);
+	psr = find_section(dev_priv, bdb, BDB_PSR);
 	if (!psr) {
 		DRM_DEBUG_KMS("No PSR BDB found.\n");
 		return;
@@ -768,7 +775,7 @@ parse_mipi(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 	/* Parse #52 for panel index used from panel_type already
 	 * parsed
 	 */
-	start = find_section(bdb, BDB_MIPI_CONFIG);
+	start = find_section(dev_priv, bdb, BDB_MIPI_CONFIG);
 	if (!start) {
 		DRM_DEBUG_KMS("No MIPI config BDB found");
 		return;
@@ -799,7 +806,7 @@ parse_mipi(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 	dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
 
 	/* Check if we have sequence block as well */
-	sequence = find_section(bdb, BDB_MIPI_SEQUENCE);
+	sequence = find_section(dev_priv, bdb, BDB_MIPI_SEQUENCE);
 	if (!sequence) {
 		DRM_DEBUG_KMS("No MIPI Sequence found, parsing complete\n");
 		return;
@@ -1023,7 +1030,7 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
 	int i, child_device_num, count;
 	u16	block_size;
 
-	p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
+	p_defs = find_section(dev_priv, bdb, BDB_GENERAL_DEFINITIONS);
 	if (!p_defs) {
 		DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n");
 		return;
diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
index 1372e39..1f76715 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -896,11 +896,14 @@ int intel_opregion_setup(struct drm_device *dev)
 	opregion->header = base;
 	opregion->asle = base + OPREGION_ASLE_OFFSET;
 
+	dev_priv->vbt_in_mailbox4 = true;
 	if (opregion->header->opregion_ver >= 2) {
-		if (opregion->asle->rvda)
+		if (opregion->asle->rvda) {
 			vbt_base = acpi_os_ioremap(opregion->asle->rvda,
 						opregion->asle->rvds);
-		else
+			dev_priv->vbt_in_mailbox4 = false;
+			dev_priv->vbt_size = opregion->asle->rvds;
+		} else
 			vbt_base = acpi_os_ioremap(asls + OPREGION_VBT_OFFSET,
 					OPREGION_SIZE - OPREGION_VBT_OFFSET);
 	} else
-- 
1.7.9.5

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[MIPI SEQ PARSING v1 PATCH 4/9] drm/i915: Added support the v3 mipi sequence block

[Deepak M]

From: vkorjani <vikas.korjani@intel.com>

The Block 53 of the VBT, which is the MIPI sequence block
has undergone a design change because of which the parsing
logic has to be changed.

The current code will handle the parsing of v3 and other
lower versions of the MIPI sequence block.

Signed-off-by: vkorjani <vikas.korjani@intel.com>
Signed-off-by: Deepak M <m.deepak@intel.com>
---
 drivers/gpu/drm/i915/intel_bios.c          |  119 +++++++++++++++++++++++-----
 drivers/gpu/drm/i915/intel_bios.h          |    8 ++
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |    7 ++
 3 files changed, 114 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 5e0ff22..858bd02 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -45,6 +45,7 @@ find_section(struct drm_i915_private *dev_priv,
 	int index = 0;
 	u32 total, current_size;
 	u8 current_id;
+	u8 version;
 
 	/* skip to first section */
 	index += bdb->header_size;
@@ -59,7 +60,17 @@ find_section(struct drm_i915_private *dev_priv,
 		current_id = *(base + index);
 		index++;
 
-		current_size = *((const u16 *)(base + index));
+		if (current_id == BDB_MIPI_SEQUENCE) {
+			version = *(base + index + 2);
+			if (version >= 3)
+				current_size = *((const u32 *)(base +
+								index + 3));
+			else
+				current_size = *((const u16 *)(base + index));
+		} else {
+			current_size = *((const u16 *)(base + index));
+		}
+
 		index += 2;
 
 		if (index + current_size > total)
@@ -748,6 +759,55 @@ static u8 *goto_next_sequence(u8 *data, int *size)
 	return data;
 }
 
+static u8 *goto_next_sequence_v3(u8 *data, int *size)
+{
+	int tmp = *size;
+	int op_size;
+
+	if (--tmp < 0)
+		return NULL;
+
+	/* Skip the panel id and the sequence size */
+	data = data + 5;
+	while (*data != 0) {
+		u8 element_type = *data++;
+
+		switch (element_type) {
+		default:
+			DRM_ERROR("Unknown element type %d\n", element_type);
+		case MIPI_SEQ_ELEM_SEND_PKT:
+		case MIPI_SEQ_ELEM_DELAY:
+		case MIPI_SEQ_ELEM_GPIO:
+		case MIPI_SEQ_ELEM_I2C:
+		case MIPI_SEQ_ELEM_SPI:
+		case MIPI_SEQ_ELEM_PMIC:
+			/*
+			 * skip by this element payload size
+			 * skip elem id, command flag and data type
+			 */
+			op_size = *data++;
+			tmp = tmp - (op_size + 1);
+			if (tmp < 0)
+				return NULL;
+
+			/* skip by len */
+			data += op_size;
+			break;
+		}
+	}
+
+	/* goto next sequence or end of block byte */
+	if (--tmp < 0)
+		return NULL;
+
+	/* Skip the end element marker */
+	data++;
+
+	/* update amount of data left for the sequence block to be parsed */
+	*size = tmp;
+	return data;
+}
+
 static void
 parse_mipi(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 {
@@ -757,7 +817,7 @@ parse_mipi(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 	const struct mipi_pps_data *pps;
 	u8 *data;
 	const u8 *seq_data;
-	int i, panel_id, seq_size;
+	int i, panel_id, panel_seq_size;
 	u16 block_size;
 
 	/* parse MIPI blocks only if LFP type is MIPI */
@@ -814,29 +874,40 @@ parse_mipi(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 
 	DRM_DEBUG_DRIVER("Found MIPI sequence block\n");
 
-	block_size = get_blocksize(sequence);
-
 	/*
 	 * parse the sequence block for individual sequences
 	 */
 	dev_priv->vbt.dsi.seq_version = sequence->version;
 
 	seq_data = &sequence->data[0];
+	if (dev_priv->vbt.dsi.seq_version >= 3) {
+		block_size = *((unsigned int *)seq_data);
+		seq_data = seq_data + 4;
+	} else
+		block_size = get_blocksize(sequence);
 
 	/*
 	 * sequence block is variable length and hence we need to parse and
 	 * get the sequence data for specific panel id
 	 */
 	for (i = 0; i < MAX_MIPI_CONFIGURATIONS; i++) {
-		panel_id = *seq_data;
-		seq_size = *((u16 *) (seq_data + 1));
+		panel_id = *seq_data++;
+		if (dev_priv->vbt.dsi.seq_version >= 3) {
+			panel_seq_size = *((u32 *)seq_data);
+			seq_data += sizeof(u32);
+		} else {
+			panel_seq_size = *((u16 *)seq_data);
+			seq_data += sizeof(u16);
+		}
+
 		if (panel_id == panel_type)
 			break;
 
-		/* skip the sequence including seq header of 3 bytes */
-		seq_data = seq_data + 3 + seq_size;
+		seq_data += panel_seq_size;
+
 		if ((seq_data - &sequence->data[0]) > block_size) {
-			DRM_ERROR("Sequence start is beyond sequence block size, corrupted sequence block\n");
+			DRM_ERROR("Sequence start is beyond seq block size\n");
+			DRM_ERROR("Corrupted sequence block\n");
 			return;
 		}
 	}
@@ -848,13 +919,14 @@ parse_mipi(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 
 	/* check if found sequence is completely within the sequence block
 	 * just being paranoid */
-	if (seq_size > block_size) {
+	if (panel_seq_size > block_size) {
 		DRM_ERROR("Corrupted sequence/size, bailing out\n");
 		return;
 	}
 
-	/* skip the panel id(1 byte) and seq size(2 bytes) */
-	dev_priv->vbt.dsi.data = kmemdup(seq_data + 3, seq_size, GFP_KERNEL);
+
+	dev_priv->vbt.dsi.data = kmemdup(seq_data, panel_seq_size, GFP_KERNEL);
+
 	if (!dev_priv->vbt.dsi.data)
 		return;
 
@@ -863,29 +935,36 @@ parse_mipi(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 	 * There are only 5 types of sequences as of now
 	 */
 	data = dev_priv->vbt.dsi.data;
-	dev_priv->vbt.dsi.size = seq_size;
+	dev_priv->vbt.dsi.size = panel_seq_size;
 
 	/* two consecutive 0x00 indicate end of all sequences */
-	while (1) {
+	while (*data != 0) {
 		int seq_id = *data;
+		int seq_size;
+
 		if (MIPI_SEQ_MAX > seq_id && seq_id > MIPI_SEQ_UNDEFINED) {
 			dev_priv->vbt.dsi.sequence[seq_id] = data;
 			DRM_DEBUG_DRIVER("Found mipi sequence - %d\n", seq_id);
 		} else {
-			DRM_ERROR("undefined sequence\n");
-			goto err;
+			DRM_ERROR("undefined sequence - %d\n", seq_id);
+			seq_size = *(data + 1);
+			if (dev_priv->vbt.dsi.seq_version >= 3) {
+				data = data + seq_size + 1;
+				continue;
+			} else
+				goto err;
 		}
 
 		/* partial parsing to skip elements */
-		data = goto_next_sequence(data, &seq_size);
+		if (dev_priv->vbt.dsi.seq_version >= 3)
+			data = goto_next_sequence_v3(data, &panel_seq_size);
+		else
+			data = goto_next_sequence(data, &panel_seq_size);
 
 		if (data == NULL) {
 			DRM_ERROR("Sequence elements going beyond block itself. Sequence block parsing failed\n");
 			goto err;
 		}
-
-		if (*data == 0)
-			break; /* end of sequence reached */
 	}
 
 	DRM_DEBUG_DRIVER("MIPI related vbt parsing complete\n");
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index 1703a83..94f1f3c 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -934,6 +934,12 @@ enum mipi_seq {
 	MIPI_SEQ_DISPLAY_ON,
 	MIPI_SEQ_DISPLAY_OFF,
 	MIPI_SEQ_DEASSERT_RESET,
+	MIPI_SEQ_BACKLIGHT_ON,
+	MIPI_SEQ_BACKLIGHT_OFF,
+	MIPI_SEQ_TEAR_ON,
+	MIPI_SEQ_TEAR_OFF,
+	MIPI_SEQ_POWER_ON,
+	MIPI_SEQ_POWER_OFF,
 	MIPI_SEQ_MAX
 };
 
@@ -943,6 +949,8 @@ enum mipi_seq_element {
 	MIPI_SEQ_ELEM_DELAY,
 	MIPI_SEQ_ELEM_GPIO,
 	MIPI_SEQ_ELEM_I2C,
+	MIPI_SEQ_ELEM_SPI,
+	MIPI_SEQ_ELEM_PMIC,
 	MIPI_SEQ_ELEM_STATUS,
 	MIPI_SEQ_ELEM_MAX
 };
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index e061a42..7e0ba74 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -315,6 +315,8 @@ static const char * const seq_name[] = {
 
 static void generic_exec_sequence(struct intel_dsi *intel_dsi, const u8 *data)
 {
+	struct drm_device *dev = intel_dsi->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	fn_mipi_elem_exec mipi_elem_exec;
 	int index;
 
@@ -325,6 +327,8 @@ static void generic_exec_sequence(struct intel_dsi *intel_dsi, const u8 *data)
 
 	/* go to the first element of the sequence */
 	data++;
+	if (dev_priv->vbt.dsi.seq_version >= 3)
+		data = data + 4;
 
 	/* parse each byte till we reach end of sequence byte - 0x00 */
 	while (1) {
@@ -338,6 +342,9 @@ static void generic_exec_sequence(struct intel_dsi *intel_dsi, const u8 *data)
 		/* goto element payload */
 		data++;
 
+		if (dev_priv->vbt.dsi.seq_version >= 3)
+			data++;
+
 		/* execute the element specific rotines */
 		data = mipi_elem_exec(intel_dsi, data);
 
-- 
1.7.9.5

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[MIPI SEQ PARSING v1 PATCH 5/9] drm/i915: Added the generic gpio sequence support and gpio table

[Deepak M]

The generic gpio is sequence is parsed from the VBT and the
GPIO table is updated with the North core, South core and
SUS core elements.

Signed-off-by: Deepak M <m.deepak@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h            |    5 +-
 drivers/gpu/drm/i915/i915_reg.h            |    5 +
 drivers/gpu/drm/i915/intel_dsi.h           |  355 ++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |  219 +++++++++++++++--
 drivers/gpu/drm/i915/intel_sideband.c      |    9 +-
 5 files changed, 573 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b38f52ee..8cf133e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3306,8 +3306,9 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val
 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
-u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
-void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
+u32 vlv_gpio_read(struct drm_i915_private *dev_priv, u8 core_offset, u32 reg);
+void vlv_gpio_write(struct drm_i915_private *dev_priv, u8 core_offset,
+			u32 reg, u32 val);
 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 313b1f9..3efea0e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -554,6 +554,11 @@
 #define   IOSF_PORT_DPIO			0x12
 #define   IOSF_PORT_DPIO_2			0x1a
 #define   IOSF_PORT_GPIO_NC			0x13
+#define   IOSF_PORT_GPIO_SC			0x48
+#define   IOSF_PORT_GPIO_SUS			0xA8
+#define   MAX_GPIO_NUM_NC			26
+#define   MAX_GPIO_NUM_SC			128
+#define   MAX_GPIO_NUM				172
 #define   IOSF_PORT_CCK				0x14
 #define   IOSF_PORT_CCU				0xA9
 #define   IOSF_PORT_GPS_CORE			0x48
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 2784ac4..13d3d22 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -34,6 +34,361 @@
 #define DSI_DUAL_LINK_FRONT_BACK	1
 #define DSI_DUAL_LINK_PIXEL_ALT		2
 
+#define HV_DDI0_HPD_GPIONC_0_PCONF0		0x4130
+#define HV_DDI0_HPD_GPIONC_0_PAD		0x4138
+#define HV_DDI0_DDC_SDA_GPIONC_1_PCONF0		0x4120
+#define HV_DDI0_DDC_SDA_GPIONC_1_PAD		0x4128
+#define HV_DDI0_DDC_SCL_GPIONC_2_PCONF0		0x4110
+#define HV_DDI0_DDC_SCL_GPIONC_2_PAD		0x4118
+#define PANEL0_VDDEN_GPIONC_3_PCONF0		0x4140
+#define PANEL0_VDDEN_GPIONC_3_PAD		0x4148
+#define PANEL0_BKLTEN_GPIONC_4_PCONF0		0x4150
+#define PANEL0_BKLTEN_GPIONC_4_PAD		0x4158
+#define PANEL0_BKLTCTL_GPIONC_5_PCONF0		0x4160
+#define PANEL0_BKLTCTL_GPIONC_5_PAD		0x4168
+#define HV_DDI1_HPD_GPIONC_6_PCONF0		0x4180
+#define HV_DDI1_HPD_GPIONC_6_PAD		0x4188
+#define HV_DDI1_DDC_SDA_GPIONC_7_PCONF0		0x4190
+#define HV_DDI1_DDC_SDA_GPIONC_7_PAD		0x4198
+#define HV_DDI1_DDC_SCL_GPIONC_8_PCONF0		0x4170
+#define HV_DDI1_DDC_SCL_GPIONC_8_PAD		0x4178
+#define PANEL1_VDDEN_GPIONC_9_PCONF0		0x4100
+#define PANEL1_VDDEN_GPIONC_9_PAD		0x4108
+#define PANEL1_BKLTEN_GPIONC_10_PCONF0		0x40E0
+#define PANEL1_BKLTEN_GPIONC_10_PAD		0x40E8
+#define PANEL1_BKLTCTL_GPIONC_11_PCONF0		0x40F0
+#define PANEL1_BKLTCTL_GPIONC_11_PAD		0x40F8
+#define GP_INTD_DSI_TE1_GPIONC_12_PCONF0	0x40C0
+#define GP_INTD_DSI_TE1_GPIONC_12_PAD		0x40C8
+#define HV_DDI2_DDC_SDA_GPIONC_13_PCONF0	0x41A0
+#define HV_DDI2_DDC_SDA_GPIONC_13_PAD		0x41A8
+#define HV_DDI2_DDC_SCL_GPIONC_14_PCONF0	0x41B0
+#define HV_DDI2_DDC_SCL_GPIONC_14_PAD		0x41B8
+#define GP_CAMERASB00_GPIONC_15_PCONF0		0x4010
+#define GP_CAMERASB00_GPIONC_15_PAD		0x4018
+#define GP_CAMERASB01_GPIONC_16_PCONF0		0x4040
+#define GP_CAMERASB01_GPIONC_16_PAD		0x4048
+#define GP_CAMERASB02_GPIONC_17_PCONF0		0x4080
+#define GP_CAMERASB02_GPIONC_17_PAD		0x4088
+#define GP_CAMERASB03_GPIONC_18_PCONF0		0x40B0
+#define GP_CAMERASB03_GPIONC_18_PAD		0x40B8
+#define GP_CAMERASB04_GPIONC_19_PCONF0		0x4000
+#define GP_CAMERASB04_GPIONC_19_PAD		0x4008
+#define GP_CAMERASB05_GPIONC_20_PCONF0		0x4030
+#define GP_CAMERASB05_GPIONC_20_PAD		0x4038
+#define GP_CAMERASB06_GPIONC_21_PCONF0		0x4060
+#define GP_CAMERASB06_GPIONC_21_PAD		0x4068
+#define GP_CAMERASB07_GPIONC_22_PCONF0		0x40A0
+#define GP_CAMERASB07_GPIONC_22_PAD		0x40A8
+#define GP_CAMERASB08_GPIONC_23_PCONF0		0x40D0
+#define GP_CAMERASB08_GPIONC_23_PAD		0x40D8
+#define GP_CAMERASB09_GPIONC_24_PCONF0		0x4020
+#define GP_CAMERASB09_GPIONC_24_PAD		0x4028
+#define GP_CAMERASB10_GPIONC_25_PCONF0		0x4050
+#define GP_CAMERASB10_GPIONC_25_PAD		0x4058
+#define GP_CAMERASB11_GPIONC_26_PCONF0		0x4090
+#define GP_CAMERASB11_GPIONC_26_PAD		0x4098
+
+#define SATA_GP0_GPIOC_0_PCONF0			0x4550
+#define SATA_GP0_GPIOC_0_PAD			0x4558
+#define SATA_GP1_GPIOC_1_PCONF0			0x4590
+#define SATA_GP1_GPIOC_1_PAD			0x4598
+#define SATA_LEDN_GPIOC_2_PCONF0		0x45D0
+#define SATA_LEDN_GPIOC_2_PAD			0x45D8
+#define PCIE_CLKREQ0B_GPIOC_3_PCONF0		0x4600
+#define PCIE_CLKREQ0B_GPIOC_3_PAD		0x4608
+#define PCIE_CLKREQ1B_GPIOC_4_PCONF0		0x4630
+#define PCIE_CLKREQ1B_GPIOC_4_PAD		0x4638
+#define PCIE_CLKREQ2B_GPIOC_5_PCONF0		0x4660
+#define PCIE_CLKREQ2B_GPIOC_5_PAD		0x4668
+#define PCIE_CLKREQ3B_GPIOC_6_PCONF0		0x4620
+#define PCIE_CLKREQ3B_GPIOC_6_PAD		0x4628
+#define PCIE_CLKREQ4B_GPIOC_7_PCONF0		0x4650
+#define PCIE_CLKREQ4B_GPIOC_7_PAD		0x4658
+#define HDA_RSTB_GPIOC_8_PCONF0			0x4220
+#define HDA_RSTB_GPIOC_8_PAD			0x4228
+#define HDA_SYNC_GPIOC_9_PCONF0			0x4250
+#define HDA_SYNC_GPIOC_9_PAD			0x4258
+#define HDA_CLK_GPIOC_10_PCONF0			0x4240
+#define HDA_CLK_GPIOC_10_PAD			0x4248
+#define HDA_SDO_GPIOC_11_PCONF0			0x4260
+#define HDA_SDO_GPIOC_11_PAD			0x4268
+#define HDA_SDI0_GPIOC_12_PCONF0		0x4270
+#define HDA_SDI0_GPIOC_12_PAD			0x4278
+#define HDA_SDI1_GPIOC_13_PCONF0		0x4230
+#define HDA_SDI1_GPIOC_13_PAD			0x4238
+#define HDA_DOCKRSTB_GPIOC_14_PCONF0		0x4280
+#define HDA_DOCKRSTB_GPIOC_14_PAD		0x4288
+#define HDA_DOCKENB_GPIOC_15_PCONF0		0x4540
+#define HDA_DOCKENB_GPIOC_15_PAD		0x4548
+#define SDMMC1_CLK_GPIOC_16_PCONF0		0x43E0
+#define SDMMC1_CLK_GPIOC_16_PAD			0x43E8
+#define SDMMC1_D0_GPIOC_17_PCONF0		0x43D0
+#define SDMMC1_D0_GPIOC_17_PAD			0x43D8
+#define SDMMC1_D1_GPIOC_18_PCONF0		0x4400
+#define SDMMC1_D1_GPIOC_18_PAD			0x4408
+#define SDMMC1_D2_GPIOC_19_PCONF0		0x43B0
+#define SDMMC1_D2_GPIOC_19_PAD			0x43B8
+#define SDMMC1_D3_CD_B_GPIOC_20_PCONF0		0x4360
+#define SDMMC1_D3_CD_B_GPIOC_20_PAD		0x4368
+#define MMC1_D4_SD_WE_GPIOC_21_PCONF0		0x4380
+#define MMC1_D4_SD_WE_GPIOC_21_PAD		0x4388
+#define MMC1_D5_GPIOC_22_PCONF0			0x43C0
+#define MMC1_D5_GPIOC_22_PAD			0x43C8
+#define MMC1_D6_GPIOC_23_PCONF0			0x4370
+#define MMC1_D6_GPIOC_23_PAD			0x4378
+#define MMC1_D7_GPIOC_24_PCONF0			0x43F0
+#define MMC1_D7_GPIOC_24_PAD			0x43F8
+#define SDMMC1_CMD_GPIOC_25_PCONF0		0x4390
+#define SDMMC1_CMD_GPIOC_25_PAD			0x4398
+#define MMC1_RESET_B_GPIOC_26_PCONF0		0x4330
+#define MMC1_RESET_B_GPIOC_26_PAD		0x4338
+#define SDMMC2_CLK_GPIOC_27_PCONF0		0x4320
+#define SDMMC2_CLK_GPIOC_27_PAD			0x4328
+#define SDMMC2_D0_GPIOC_28_PCONF0		0x4350
+#define SDMMC2_D0_GPIOC_28_PAD			0x4358
+#define SDMMC2_D1_GPIOC_29_PCONF0		0x42F0
+#define SDMMC2_D1_GPIOC_29_PAD			0x42F8
+#define SDMMC2_D2_GPIOC_30_PCONF0		0x4340
+#define SDMMC2_D2_GPIOC_30_PAD			0x4348
+#define SDMMC2_D3_CD_B_GPIOC_31_PCONF0		0x4310
+#define SDMMC2_D3_CD_B_GPIOC_31_PAD		0x4318
+#define SDMMC2_CMD_GPIOC_32_PCONF0		0x4300
+#define SDMMC2_CMD_GPIOC_32_PAD			0x4308
+#define SDMMC3_CLK_GPIOC_33_PCONF0		0x42B0
+#define SDMMC3_CLK_GPIOC_33_PAD			0x42B8
+#define SDMMC3_D0_GPIOC_34_PCONF0		0x42E0
+#define SDMMC3_D0_GPIOC_34_PAD			0x42E8
+#define SDMMC3_D1_GPIOC_35_PCONF0		0x4290
+#define SDMMC3_D1_GPIOC_35_PAD			0x4298
+#define SDMMC3_D2_GPIOC_36_PCONF0		0x42D0
+#define SDMMC3_D2_GPIOC_36_PAD			0x42D8
+#define SDMMC3_D3_GPIOC_37_PCONF0		0x42A0
+#define SDMMC3_D3_GPIOC_37_PAD			0x42A8
+#define SDMMC3_CD_B_GPIOC_38_PCONF0		0x43A0
+#define SDMMC3_CD_B_GPIOC_38_PAD		0x43A8
+#define SDMMC3_CMD_GPIOC_39_PCONF0		0x42C0
+#define SDMMC3_CMD_GPIOC_39_PAD			0x42C8
+#define SDMMC3_1P8_EN_GPIOC_40_PCONF0		0x45F0
+#define SDMMC3_1P8_EN_GPIOC_40_PAD		0x45F8
+#define SDMMC3_PWR_EN_B_GPIOC_41_PCONF0		0x4690
+#define SDMMC3_PWR_EN_B_GPIOC_41_PAD		0x4698
+#define LPC_AD0_GPIOC_42_PCONF0			0x4460
+#define LPC_AD0_GPIOC_42_PAD			0x4468
+#define LPC_AD1_GPIOC_43_PCONF0			0x4440
+#define LPC_AD1_GPIOC_43_PAD			0x4448
+#define LPC_AD2_GPIOC_44_PCONF0			0x4430
+#define LPC_AD2_GPIOC_44_PAD			0x4438
+#define LPC_AD3_GPIOC_45_PCONF0			0x4420
+#define LPC_AD3_GPIOC_45_PAD			0x4428
+#define LPC_FRAMEB_GPIOC_46_PCONF0		0x4450
+#define LPC_FRAMEB_GPIOC_46_PAD			0x4458
+#define LPC_CLKOUT0_GPIOC_47_PCONF0		0x4470
+#define LPC_CLKOUT0_GPIOC_47_PAD		0x4478
+#define LPC_CLKOUT1_GPIOC_48_PCONF0		0x4410
+#define LPC_CLKOUT1_GPIOC_48_PAD		0x4418
+#define LPC_CLKRUNB_GPIOC_49_PCONF0		0x4480
+#define LPC_CLKRUNB_GPIOC_49_PAD		0x4488
+#define ILB_SERIRQ_GPIOC_50_PCONF0		0x4560
+#define ILB_SERIRQ_GPIOC_50_PAD			0x4568
+#define SMB_DATA_GPIOC_51_PCONF0		0x45A0
+#define SMB_DATA_GPIOC_51_PAD			0x45A8
+#define SMB_CLK_GPIOC_52_PCONF0			0x4580
+#define SMB_CLK_GPIOC_52_PAD			0x4588
+#define SMB_ALERTB_GPIOC_53_PCONF0		0x45C0
+#define SMB_ALERTB_GPIOC_53_PAD			0x45C8
+#define SPKR_GPIOC_54_PCONF0			0x4670
+#define SPKR_GPIOC_54_PAD			0x4678
+#define MHSI_ACDATA_GPIOC_55_PCONF0		0x44D0
+#define MHSI_ACDATA_GPIOC_55_PAD		0x44D8
+#define MHSI_ACFLAG_GPIOC_56_PCONF0		0x44F0
+#define MHSI_ACFLAG_GPIOC_56_PAD		0x44F8
+#define MHSI_ACREADY_GPIOC_57_PCONF0		0x4530
+#define MHSI_ACREADY_GPIOC_57_PAD		0x4538
+#define MHSI_ACWAKE_GPIOC_58_PCONF0		0x44E0
+#define MHSI_ACWAKE_GPIOC_58_PAD		0x44E8
+#define MHSI_CADATA_GPIOC_59_PCONF0		0x4510
+#define MHSI_CADATA_GPIOC_59_PAD		0x4518
+#define MHSI_CAFLAG_GPIOC_60_PCONF0		0x4500
+#define MHSI_CAFLAG_GPIOC_60_PAD		0x4508
+#define MHSI_CAREADY_GPIOC_61_PCONF0		0x4520
+#define MHSI_CAREADY_GPIOC_61_PAD		0x4528
+#define GP_SSP_2_CLK_GPIOC_62_PCONF0		0x40D0
+#define GP_SSP_2_CLK_GPIOC_62_PAD		0x40D8
+#define GP_SSP_2_FS_GPIOC_63_PCONF0		0x40C0
+#define GP_SSP_2_FS_GPIOC_63_PAD		0x40C8
+#define GP_SSP_2_RXD_GPIOC_64_PCONF0		0x40F0
+#define GP_SSP_2_RXD_GPIOC_64_PAD		0x40F8
+#define GP_SSP_2_TXD_GPIOC_65_PCONF0		0x40E0
+#define GP_SSP_2_TXD_GPIOC_65_PAD		0x40E8
+#define SPI1_CS0_B_GPIOC_66_PCONF0		0x4110
+#define SPI1_CS0_B_GPIOC_66_PAD			0x4118
+#define SPI1_MISO_GPIOC_67_PCONF0		0x4120
+#define SPI1_MISO_GPIOC_67_PAD			0x4128
+#define SPI1_MOSI_GPIOC_68_PCONF0		0x4130
+#define SPI1_MOSI_GPIOC_68_PAD			0x4138
+#define SPI1_CLK_GPIOC_69_PCONF0		0x4100
+#define SPI1_CLK_GPIOC_69_PAD			0x4108
+#define UART1_RXD_GPIOC_70_PCONF0		0x4020
+#define UART1_RXD_GPIOC_70_PAD			0x4028
+#define UART1_TXD_GPIOC_71_PCONF0		0x4010
+#define UART1_TXD_GPIOC_71_PAD			0x4018
+#define UART1_RTS_B_GPIOC_72_PCONF0		0x4000
+#define UART1_RTS_B_GPIOC_72_PAD		0x4008
+#define UART1_CTS_B_GPIOC_73_PCONF0		0x4040
+#define UART1_CTS_B_GPIOC_73_PAD		0x4048
+#define UART2_RXD_GPIOC_74_PCONF0		0x4060
+#define UART2_RXD_GPIOC_74_PAD			0x4068
+#define UART2_TXD_GPIOC_75_PCONF0		0x4070
+#define UART2_TXD_GPIOC_75_PAD			0x4078
+#define UART2_RTS_B_GPIOC_76_PCONF0		0x4090
+#define UART2_RTS_B_GPIOC_76_PAD		0x4098
+#define UART2_CTS_B_GPIOC_77_PCONF0		0x4080
+#define UART2_CTS_B_GPIOC_77_PAD		0x4088
+#define I2C0_SDA_GPIOC_78_PCONF0		0x4210
+#define I2C0_SDA_GPIOC_78_PAD			0x4218
+#define I2C0_SCL_GPIOC_79_PCONF0		0x4200
+#define I2C0_SCL_GPIOC_79_PAD			0x4208
+#define I2C1_SDA_GPIOC_80_PCONF0		0x41F0
+#define I2C1_SDA_GPIOC_80_PAD			0x41F8
+#define I2C1_SCL_GPIOC_81_PCONF0		0x41E0
+#define I2C1_SCL_GPIOC_81_PAD			0x41E8
+#define I2C2_SDA_GPIOC_82_PCONF0		0x41D0
+#define I2C2_SDA_GPIOC_82_PAD			0x41D8
+#define I2C2_SCL_GPIOC_83_PCONF0		0x41B0
+#define I2C2_SCL_GPIOC_83_PAD			0x41B8
+#define I2C3_SDA_GPIOC_84_PCONF0		0x4190
+#define I2C2_SCL_GPIOC_83_PAD			0x41B8
+#define I2C3_SDA_GPIOC_84_PCONF0		0x4190
+#define I2C3_SDA_GPIOC_84_PAD			0x4198
+#define I2C3_SCL_GPIOC_85_PCONF0		0x41C0
+#define I2C3_SCL_GPIOC_85_PAD			0x41C8
+#define I2C4_SDA_GPIOC_86_PCONF0		0x41A0
+#define I2C4_SDA_GPIOC_86_PAD			0x41A8
+#define I2C4_SCL_GPIOC_87_PCONF0		0x4170
+#define I2C4_SCL_GPIOC_87_PAD			0x4178
+#define I2C5_SDA_GPIOC_88_PCONF0		0x4150
+#define I2C5_SDA_GPIOC_88_PAD			0x4158
+#define I2C5_SCL_GPIOC_89_PCONF0		0x4140
+#define I2C5_SCL_GPIOC_89_PAD			0x4148
+#define I2C6_SDA_GPIOC_90_PCONF0		0x4180
+#define I2C6_SDA_GPIOC_90_PAD			0x4188
+#define I2C6_SCL_GPIOC_91_PCONF0		0x4160
+#define I2C6_SCL_GPIOC_91_PAD			0x4168
+#define I2C_NFC_SDA_GPIOC_92_PCONF0		0x4050
+#define I2C_NFC_SDA_GPIOC_92_PAD		0x4058
+#define I2C_NFC_SCL_GPIOC_93_PCONF0		0x4030
+#define I2C_NFC_SCL_GPIOC_93_PAD		0x4038
+#define PWM0_GPIOC_94_PCONF0			0x40A0
+#define PWM0_GPIOC_94_PAD			0x40A8
+#define PWM1_GPIOC_95_PCONF0			0x40B0
+#define PWM1_GPIOC_95_PAD			0x40B8
+#define PLT_CLK0_GPIOC_96_PCONF0		0x46A0
+#define PLT_CLK0_GPIOC_96_PAD			0x46A8
+#define PLT_CLK1_GPIOC_97_PCONF0		0x4570
+#define PLT_CLK1_GPIOC_97_PAD			0x4578
+#define PLT_CLK2_GPIOC_98_PCONF0		0x45B0
+#define PLT_CLK2_GPIOC_98_PAD			0x45B8
+#define PLT_CLK3_GPIOC_99_PCONF0		0x4680
+#define PLT_CLK3_GPIOC_99_PAD			0x4688
+#define PLT_CLK4_GPIOC_100_PCONF0		0x4610
+#define PLT_CLK4_GPIOC_100_PAD			0x4618
+#define PLT_CLK5_GPIOC_101_PCONF0		0x4640
+#define PLT_CLK5_GPIOC_101_PAD			0x4648
+
+#define GPIO_SUS0_GPIO_SUS0_PCONF0		0x41D0
+#define GPIO_SUS0_GPIO_SUS0_PAD			0x41D8
+#define GPIO_SUS1_GPIO_SUS1_PCONF0		0x4210
+#define GPIO_SUS1_GPIO_SUS1_PAD			0x4218
+#define GPIO_SUS2_GPIO_SUS2_PCONF0		0x41E0
+#define GPIO_SUS2_GPIO_SUS2_PAD			0x41E8
+#define GPIO_SUS3_GPIO_SUS3_PCONF0		0x41F0
+#define GPIO_SUS3_GPIO_SUS3_PAD			0x41F8
+#define GPIO_SUS4_GPIO_SUS4_PCONF0		0x4200
+#define GPIO_SUS4_GPIO_SUS4_PAD			0x4208
+#define GPIO_SUS5_GPIO_SUS5_PCONF0		0x4220
+#define GPIO_SUS5_GPIO_SUS5_PAD			0x4228
+#define GPIO_SUS6_GPIO_SUS6_PCONF0		0x4240
+#define GPIO_SUS6_GPIO_SUS6_PAD			0x4248
+#define GPIO_SUS7_GPIO_SUS7_PCONF0		0x4230
+#define GPIO_SUS7_GPIO_SUS7_PAD			0x4238
+#define SEC_GPIO_SUS8_GPIO_SUS8_PCONF0		0x4260
+#define SEC_GPIO_SUS8_GPIO_SUS8_PAD		0x4268
+#define SEC_GPIO_SUS9_GPIO_SUS9_PCONF0		0x4250
+#define SEC_GPIO_SUS9_GPIO_SUS9_PAD		0x4258
+#define SEC_GPIO_SUS10_GPIO_SUS10_PCONF0	0x4120
+#define SEC_GPIO_SUS10_GPIO_SUS10_PAD		0x4128
+#define SUSPWRDNACK_GPIOS_11_PCONF0		0x4070
+#define SUSPWRDNACK_GPIOS_11_PAD		0x4078
+#define PMU_SUSCLK_GPIOS_12_PCONF0		0x40B0
+#define PMU_SUSCLK_GPIOS_12_PAD			0x40B8
+#define PMU_SLP_S0IX_B_GPIOS_13_PCONF0		0x4140
+#define PMU_SLP_S0IX_B_GPIOS_13_PAD		0x4148
+#define PMU_SLP_LAN_B_GPIOS_14_PCONF0		0x4110
+#define PMU_SLP_LAN_B_GPIOS_14_PAD		0x4118
+#define PMU_WAKE_B_GPIOS_15_PCONF0		0x4010
+#define PMU_WAKE_B_GPIOS_15_PAD			0x4018
+#define PMU_PWRBTN_B_GPIOS_16_PCONF0		0x4080
+#define PMU_PWRBTN_B_GPIOS_16_PAD		0x4088
+#define PMU_WAKE_LAN_B_GPIOS_17_PCONF0		0x40A0
+#define PMU_WAKE_LAN_B_GPIOS_17_PAD		0x40A8
+#define SUS_STAT_B_GPIOS_18_PCONF0		0x4130
+#define SUS_STAT_B_GPIOS_18_PAD			0x4138
+#define USB_OC0_B_GPIOS_19_PCONF0		0x40C0
+#define USB_OC0_B_GPIOS_19_PAD			0x40C8
+#define USB_OC1_B_GPIOS_20_PCONF0		0x4000
+#define USB_OC1_B_GPIOS_20_PAD			0x4008
+#define SPI_CS1_B_GPIOS_21_PCONF0		0x4020
+#define SPI_CS1_B_GPIOS_21_PAD			0x4028
+#define GPIO_DFX0_GPIOS_22_PCONF0		0x4170
+#define GPIO_DFX0_GPIOS_22_PAD			0x4178
+#define GPIO_DFX1_GPIOS_23_PCONF0		0x4270
+#define GPIO_DFX1_GPIOS_23_PAD			0x4278
+#define GPIO_DFX2_GPIOS_24_PCONF0		0x41C0
+#define GPIO_DFX2_GPIOS_24_PAD			0x41C8
+#define GPIO_DFX3_GPIOS_25_PCONF0		0x41B0
+#define GPIO_DFX3_GPIOS_25_PAD			0x41B8
+#define GPIO_DFX4_GPIOS_26_PCONF0		0x4160
+#define GPIO_DFX4_GPIOS_26_PAD			0x4168
+#define GPIO_DFX5_GPIOS_27_PCONF0		0x4150
+#define GPIO_DFX5_GPIOS_27_PAD			0x4158
+#define GPIO_DFX6_GPIOS_28_PCONF0		0x4180
+#define GPIO_DFX6_GPIOS_28_PAD			0x4188
+#define GPIO_DFX7_GPIOS_29_PCONF0		0x4190
+#define GPIO_DFX7_GPIOS_29_PAD			0x4198
+#define GPIO_DFX8_GPIOS_30_PCONF0		0x41A0
+#define GPIO_DFX8_GPIOS_30_PAD			0x41A8
+#define USB_ULPI_0_CLK_GPIOS_31_PCONF0		0x4330
+#define USB_ULPI_0_CLK_GPIOS_31_PAD		0x4338
+#define USB_ULPI_0_DATA0_GPIOS_32_PCONF0	0x4380
+#define USB_ULPI_0_DATA0_GPIOS_32_PAD		0x4388
+#define USB_ULPI_0_DATA1_GPIOS_33_PCONF0	0x4360
+#define USB_ULPI_0_DATA1_GPIOS_33_PAD		0x4368
+#define USB_ULPI_0_DATA2_GPIOS_34_PCONF0	0x4310
+#define USB_ULPI_0_DATA2_GPIOS_34_PAD		0x4318
+#define USB_ULPI_0_DATA3_GPIOS_35_PCONF0	0x4370
+#define USB_ULPI_0_DATA3_GPIOS_35_PAD		0x4378
+#define USB_ULPI_0_DATA4_GPIOS_36_PCONF0	0x4300
+#define USB_ULPI_0_DATA4_GPIOS_36_PAD		0x4308
+#define USB_ULPI_0_DATA5_GPIOS_37_PCONF0	0x4390
+#define USB_ULPI_0_DATA5_GPIOS_37_PAD		0x4398
+#define USB_ULPI_0_DATA6_GPIOS_38_PCONF0	0x4320
+#define USB_ULPI_0_DATA6_GPIOS_38_PAD		0x4328
+#define USB_ULPI_0_DATA7_GPIOS_39_PCONF0	0x43A0
+#define USB_ULPI_0_DATA7_GPIOS_39_PAD		0x43A8
+#define USB_ULPI_0_DIR_GPIOS_40_PCONF0		0x4340
+#define USB_ULPI_0_DIR_GPIOS_40_PAD		0x4348
+#define USB_ULPI_0_NXT_GPIOS_41_PCONF0		0x4350
+#define USB_ULPI_0_NXT_GPIOS_41_PAD		0x4358
+#define USB_ULPI_0_STP_GPIOS_42_PCONF0		0x43B0
+#define USB_ULPI_0_STP_GPIOS_42_PAD		0x43B8
+#define USB_ULPI_0_REFCLK_GPIOS_43_PCONF0	0x4280
+#define USB_ULPI_0_REFCLK_GPIOS_43_PAD		0x4288
+
+#define PMIC_PANEL_EN		0x52
+#define PMIC_PWM_EN		0x51
+#define PMIC_BKL_EN		0x4B
+#define PMIC_PWM_LEVEL		0x4E
 struct intel_dsi_host;
 
 struct intel_dsi {
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 7e0ba74..f2ea875 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -91,18 +91,181 @@ struct gpio_table {
 };
 
 static struct gpio_table gtable[] = {
-	{ GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
-	{ GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
-	{ GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
-	{ GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 },
-	{ GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 },
-	{ GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 },
-	{ GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
-	{ GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
-	{ GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
-	{ GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
-	{ GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
-	{ GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
+	{HV_DDI0_HPD_GPIONC_0_PCONF0, HV_DDI0_HPD_GPIONC_0_PAD, 0},
+	{HV_DDI0_DDC_SDA_GPIONC_1_PCONF0, HV_DDI0_DDC_SDA_GPIONC_1_PAD, 0},
+	{HV_DDI0_DDC_SCL_GPIONC_2_PCONF0, HV_DDI0_DDC_SCL_GPIONC_2_PAD, 0},
+	{PANEL0_VDDEN_GPIONC_3_PCONF0, PANEL0_VDDEN_GPIONC_3_PAD, 0},
+	{PANEL0_BKLTEN_GPIONC_4_PCONF0, PANEL0_BKLTEN_GPIONC_4_PAD, 0},
+	{PANEL0_BKLTCTL_GPIONC_5_PCONF0, PANEL0_BKLTCTL_GPIONC_5_PAD, 0},
+	{HV_DDI1_HPD_GPIONC_6_PCONF0, HV_DDI1_HPD_GPIONC_6_PAD, 0},
+	{HV_DDI1_DDC_SDA_GPIONC_7_PCONF0, HV_DDI1_DDC_SDA_GPIONC_7_PAD, 0},
+	{HV_DDI1_DDC_SCL_GPIONC_8_PCONF0, HV_DDI1_DDC_SCL_GPIONC_8_PAD, 0},
+	{PANEL1_VDDEN_GPIONC_9_PCONF0, PANEL1_VDDEN_GPIONC_9_PAD, 0},
+	{PANEL1_BKLTEN_GPIONC_10_PCONF0, PANEL1_BKLTEN_GPIONC_10_PAD, 0},
+	{PANEL1_BKLTCTL_GPIONC_11_PCONF0, PANEL1_BKLTCTL_GPIONC_11_PAD, 0},
+	{GP_INTD_DSI_TE1_GPIONC_12_PCONF0, GP_INTD_DSI_TE1_GPIONC_12_PAD, 0},
+	{HV_DDI2_DDC_SDA_GPIONC_13_PCONF0, HV_DDI2_DDC_SDA_GPIONC_13_PAD, 0},
+	{HV_DDI2_DDC_SCL_GPIONC_14_PCONF0, HV_DDI2_DDC_SCL_GPIONC_14_PAD, 0},
+	{GP_CAMERASB00_GPIONC_15_PCONF0, GP_CAMERASB00_GPIONC_15_PAD, 0},
+	{GP_CAMERASB01_GPIONC_16_PCONF0, GP_CAMERASB01_GPIONC_16_PAD, 0},
+	{GP_CAMERASB02_GPIONC_17_PCONF0, GP_CAMERASB02_GPIONC_17_PAD, 0},
+	{GP_CAMERASB03_GPIONC_18_PCONF0, GP_CAMERASB03_GPIONC_18_PAD, 0},
+	{GP_CAMERASB04_GPIONC_19_PCONF0, GP_CAMERASB04_GPIONC_19_PAD, 0},
+	{GP_CAMERASB05_GPIONC_20_PCONF0, GP_CAMERASB05_GPIONC_20_PAD, 0},
+	{GP_CAMERASB06_GPIONC_21_PCONF0, GP_CAMERASB06_GPIONC_21_PAD, 0},
+	{GP_CAMERASB07_GPIONC_22_PCONF0, GP_CAMERASB07_GPIONC_22_PAD, 0},
+	{GP_CAMERASB08_GPIONC_23_PCONF0, GP_CAMERASB08_GPIONC_23_PAD, 0},
+	{GP_CAMERASB09_GPIONC_24_PCONF0, GP_CAMERASB09_GPIONC_24_PAD, 0},
+	{GP_CAMERASB10_GPIONC_25_PCONF0, GP_CAMERASB10_GPIONC_25_PAD, 0},
+	{GP_CAMERASB11_GPIONC_26_PCONF0, GP_CAMERASB11_GPIONC_26_PAD, 0},
+
+	{SATA_GP0_GPIOC_0_PCONF0, SATA_GP0_GPIOC_0_PAD, 0},
+	{SATA_GP1_GPIOC_1_PCONF0, SATA_GP1_GPIOC_1_PAD, 0},
+	{SATA_LEDN_GPIOC_2_PCONF0, SATA_LEDN_GPIOC_2_PAD, 0},
+	{PCIE_CLKREQ0B_GPIOC_3_PCONF0, PCIE_CLKREQ0B_GPIOC_3_PAD, 0},
+	{PCIE_CLKREQ1B_GPIOC_4_PCONF0, PCIE_CLKREQ1B_GPIOC_4_PAD, 0},
+	{PCIE_CLKREQ2B_GPIOC_5_PCONF0, PCIE_CLKREQ2B_GPIOC_5_PAD, 0},
+	{PCIE_CLKREQ3B_GPIOC_6_PCONF0, PCIE_CLKREQ3B_GPIOC_6_PAD, 0},
+	{PCIE_CLKREQ4B_GPIOC_7_PCONF0, PCIE_CLKREQ4B_GPIOC_7_PAD, 0},
+	{HDA_RSTB_GPIOC_8_PCONF0, HDA_RSTB_GPIOC_8_PAD, 0},
+	{HDA_SYNC_GPIOC_9_PCONF0, HDA_SYNC_GPIOC_9_PAD, 0},
+	{HDA_CLK_GPIOC_10_PCONF0, HDA_CLK_GPIOC_10_PAD, 0},
+	{HDA_SDO_GPIOC_11_PCONF0, HDA_SDO_GPIOC_11_PAD, 0},
+	{HDA_SDI0_GPIOC_12_PCONF0, HDA_SDI0_GPIOC_12_PAD, 0},
+	{HDA_SDI1_GPIOC_13_PCONF0, HDA_SDI1_GPIOC_13_PAD, 0},
+	{HDA_DOCKRSTB_GPIOC_14_PCONF0, HDA_DOCKRSTB_GPIOC_14_PAD, 0},
+	{HDA_DOCKENB_GPIOC_15_PCONF0, HDA_DOCKENB_GPIOC_15_PAD, 0},
+	{SDMMC1_CLK_GPIOC_16_PCONF0, SDMMC1_CLK_GPIOC_16_PAD, 0},
+	{SDMMC1_D0_GPIOC_17_PCONF0, SDMMC1_D0_GPIOC_17_PAD, 0},
+	{SDMMC1_D1_GPIOC_18_PCONF0, SDMMC1_D1_GPIOC_18_PAD, 0},
+	{SDMMC1_D2_GPIOC_19_PCONF0, SDMMC1_D2_GPIOC_19_PAD, 0},
+	{SDMMC1_D3_CD_B_GPIOC_20_PCONF0, SDMMC1_D3_CD_B_GPIOC_20_PAD, 0},
+	{MMC1_D4_SD_WE_GPIOC_21_PCONF0, MMC1_D4_SD_WE_GPIOC_21_PAD, 0},
+	{MMC1_D5_GPIOC_22_PCONF0, MMC1_D5_GPIOC_22_PAD, 0},
+	{MMC1_D6_GPIOC_23_PCONF0, MMC1_D6_GPIOC_23_PAD, 0},
+	{MMC1_D7_GPIOC_24_PCONF0, MMC1_D7_GPIOC_24_PAD, 0},
+	{SDMMC1_CMD_GPIOC_25_PCONF0, SDMMC1_CMD_GPIOC_25_PAD, 0},
+	{MMC1_RESET_B_GPIOC_26_PCONF0, MMC1_RESET_B_GPIOC_26_PAD, 0},
+	{SDMMC2_CLK_GPIOC_27_PCONF0, SDMMC2_CLK_GPIOC_27_PAD, 0},
+	{SDMMC2_D0_GPIOC_28_PCONF0, SDMMC2_D0_GPIOC_28_PAD, 0},
+	{SDMMC2_D1_GPIOC_29_PCONF0, SDMMC2_D1_GPIOC_29_PAD, 0},
+	{SDMMC2_D2_GPIOC_30_PCONF0, SDMMC2_D2_GPIOC_30_PAD, 0},
+	{SDMMC2_D3_CD_B_GPIOC_31_PCONF0, SDMMC2_D3_CD_B_GPIOC_31_PAD, 0},
+	{SDMMC2_CMD_GPIOC_32_PCONF0, SDMMC2_CMD_GPIOC_32_PAD, 0},
+	{SDMMC3_CLK_GPIOC_33_PCONF0, SDMMC3_CLK_GPIOC_33_PAD, 0},
+	{SDMMC3_D0_GPIOC_34_PCONF0, SDMMC3_D0_GPIOC_34_PAD, 0},
+	{SDMMC3_D1_GPIOC_35_PCONF0, SDMMC3_D1_GPIOC_35_PAD, 0},
+	{SDMMC3_D2_GPIOC_36_PCONF0, SDMMC3_D2_GPIOC_36_PAD, 0},
+	{SDMMC3_D3_GPIOC_37_PCONF0, SDMMC3_D3_GPIOC_37_PAD, 0},
+	{SDMMC3_CD_B_GPIOC_38_PCONF0, SDMMC3_CD_B_GPIOC_38_PAD, 0},
+	{SDMMC3_CMD_GPIOC_39_PCONF0, SDMMC3_CMD_GPIOC_39_PAD, 0},
+	{SDMMC3_1P8_EN_GPIOC_40_PCONF0, SDMMC3_1P8_EN_GPIOC_40_PAD, 0},
+	{SDMMC3_PWR_EN_B_GPIOC_41_PCONF0, SDMMC3_PWR_EN_B_GPIOC_41_PAD, 0},
+	{LPC_AD0_GPIOC_42_PCONF0, LPC_AD0_GPIOC_42_PAD, 0},
+	{LPC_AD1_GPIOC_43_PCONF0, LPC_AD1_GPIOC_43_PAD, 0},
+	{LPC_AD2_GPIOC_44_PCONF0, LPC_AD2_GPIOC_44_PAD, 0},
+	{LPC_AD3_GPIOC_45_PCONF0, LPC_AD3_GPIOC_45_PAD, 0},
+	{LPC_FRAMEB_GPIOC_46_PCONF0, LPC_FRAMEB_GPIOC_46_PAD, 0},
+	{LPC_CLKOUT0_GPIOC_47_PCONF0, LPC_CLKOUT0_GPIOC_47_PAD, 0},
+	{LPC_CLKOUT1_GPIOC_48_PCONF0, LPC_CLKOUT1_GPIOC_48_PAD, 0},
+	{LPC_CLKRUNB_GPIOC_49_PCONF0, LPC_CLKRUNB_GPIOC_49_PAD, 0},
+	{ILB_SERIRQ_GPIOC_50_PCONF0, ILB_SERIRQ_GPIOC_50_PAD, 0},
+	{SMB_DATA_GPIOC_51_PCONF0, SMB_DATA_GPIOC_51_PAD, 0},
+	{SMB_CLK_GPIOC_52_PCONF0, SMB_CLK_GPIOC_52_PAD, 0},
+	{SMB_ALERTB_GPIOC_53_PCONF0, SMB_ALERTB_GPIOC_53_PAD, 0},
+	{SPKR_GPIOC_54_PCONF0, SPKR_GPIOC_54_PAD, 0},
+	{MHSI_ACDATA_GPIOC_55_PCONF0, MHSI_ACDATA_GPIOC_55_PAD, 0},
+	{MHSI_ACFLAG_GPIOC_56_PCONF0, MHSI_ACFLAG_GPIOC_56_PAD, 0},
+	{MHSI_ACREADY_GPIOC_57_PCONF0, MHSI_ACREADY_GPIOC_57_PAD, 0},
+	{MHSI_ACWAKE_GPIOC_58_PCONF0, MHSI_ACWAKE_GPIOC_58_PAD, 0},
+	{MHSI_CADATA_GPIOC_59_PCONF0, MHSI_CADATA_GPIOC_59_PAD, 0},
+	{MHSI_CAFLAG_GPIOC_60_PCONF0, MHSI_CAFLAG_GPIOC_60_PAD, 0},
+	{MHSI_CAREADY_GPIOC_61_PCONF0, MHSI_CAREADY_GPIOC_61_PAD, 0},
+	{GP_SSP_2_CLK_GPIOC_62_PCONF0, GP_SSP_2_CLK_GPIOC_62_PAD, 0},
+	{GP_SSP_2_FS_GPIOC_63_PCONF0, GP_SSP_2_FS_GPIOC_63_PAD, 0},
+	{GP_SSP_2_RXD_GPIOC_64_PCONF0, GP_SSP_2_RXD_GPIOC_64_PAD, 0},
+	{GP_SSP_2_TXD_GPIOC_65_PCONF0, GP_SSP_2_TXD_GPIOC_65_PAD, 0},
+	{SPI1_CS0_B_GPIOC_66_PCONF0, SPI1_CS0_B_GPIOC_66_PAD, 0},
+	{SPI1_MISO_GPIOC_67_PCONF0, SPI1_MISO_GPIOC_67_PAD, 0},
+	{SPI1_MOSI_GPIOC_68_PCONF0, SPI1_MOSI_GPIOC_68_PAD, 0},
+	{SPI1_CLK_GPIOC_69_PCONF0, SPI1_CLK_GPIOC_69_PAD, 0},
+	{UART1_RXD_GPIOC_70_PCONF0, UART1_RXD_GPIOC_70_PAD, 0},
+	{UART1_TXD_GPIOC_71_PCONF0, UART1_TXD_GPIOC_71_PAD, 0},
+	{UART1_RTS_B_GPIOC_72_PCONF0, UART1_RTS_B_GPIOC_72_PAD, 0},
+	{UART1_CTS_B_GPIOC_73_PCONF0, UART1_CTS_B_GPIOC_73_PAD, 0},
+	{UART2_RXD_GPIOC_74_PCONF0, UART2_RXD_GPIOC_74_PAD, 0},
+	{UART2_TXD_GPIOC_75_PCONF0, UART2_TXD_GPIOC_75_PAD, 0},
+	{UART2_RTS_B_GPIOC_76_PCONF0, UART2_RTS_B_GPIOC_76_PAD, 0},
+	{UART2_CTS_B_GPIOC_77_PCONF0, UART2_CTS_B_GPIOC_77_PAD, 0},
+	{I2C0_SDA_GPIOC_78_PCONF0, I2C0_SDA_GPIOC_78_PAD, 0},
+	{I2C0_SCL_GPIOC_79_PCONF0, I2C0_SCL_GPIOC_79_PAD, 0},
+	{I2C1_SDA_GPIOC_80_PCONF0, I2C1_SDA_GPIOC_80_PAD, 0},
+	{I2C1_SCL_GPIOC_81_PCONF0, I2C1_SCL_GPIOC_81_PAD, 0},
+	{I2C2_SDA_GPIOC_82_PCONF0, I2C2_SDA_GPIOC_82_PAD, 0},
+	{I2C2_SCL_GPIOC_83_PCONF0, I2C2_SCL_GPIOC_83_PAD, 0},
+	{I2C3_SDA_GPIOC_84_PCONF0, I2C3_SDA_GPIOC_84_PAD, 0},
+	{I2C3_SCL_GPIOC_85_PCONF0, I2C3_SCL_GPIOC_85_PAD, 0},
+	{I2C4_SDA_GPIOC_86_PCONF0, I2C4_SDA_GPIOC_86_PAD, 0},
+	{I2C4_SCL_GPIOC_87_PCONF0, I2C4_SCL_GPIOC_87_PAD, 0},
+	{I2C5_SDA_GPIOC_88_PCONF0, I2C5_SDA_GPIOC_88_PAD, 0},
+	{I2C5_SCL_GPIOC_89_PCONF0, I2C5_SCL_GPIOC_89_PAD, 0},
+	{I2C6_SDA_GPIOC_90_PCONF0, I2C6_SDA_GPIOC_90_PAD, 0},
+	{I2C6_SCL_GPIOC_91_PCONF0, I2C6_SCL_GPIOC_91_PAD, 0},
+	{I2C_NFC_SDA_GPIOC_92_PCONF0, I2C_NFC_SDA_GPIOC_92_PAD, 0},
+	{I2C_NFC_SCL_GPIOC_93_PCONF0, I2C_NFC_SCL_GPIOC_93_PAD, 0},
+	{PWM0_GPIOC_94_PCONF0, PWM0_GPIOC_94_PAD, 0},
+	{PWM1_GPIOC_95_PCONF0, PWM1_GPIOC_95_PAD, 0},
+	{PLT_CLK0_GPIOC_96_PCONF0, PLT_CLK0_GPIOC_96_PAD, 0},
+	{PLT_CLK1_GPIOC_97_PCONF0, PLT_CLK1_GPIOC_97_PAD, 0},
+	{PLT_CLK2_GPIOC_98_PCONF0, PLT_CLK2_GPIOC_98_PAD, 0},
+	{PLT_CLK3_GPIOC_99_PCONF0, PLT_CLK3_GPIOC_99_PAD, 0},
+	{PLT_CLK4_GPIOC_100_PCONF0, PLT_CLK4_GPIOC_100_PAD, 0},
+	{PLT_CLK5_GPIOC_101_PCONF0, PLT_CLK5_GPIOC_101_PAD, 0},
+
+	{GPIO_SUS0_GPIO_SUS0_PCONF0, GPIO_SUS0_GPIO_SUS0_PAD, 0},
+	{GPIO_SUS1_GPIO_SUS1_PCONF0, GPIO_SUS1_GPIO_SUS1_PAD, 0},
+	{GPIO_SUS2_GPIO_SUS2_PCONF0, GPIO_SUS2_GPIO_SUS2_PAD, 0},
+	{GPIO_SUS3_GPIO_SUS3_PCONF0, GPIO_SUS3_GPIO_SUS3_PAD, 0},
+	{GPIO_SUS4_GPIO_SUS4_PCONF0, GPIO_SUS4_GPIO_SUS4_PAD, 0},
+	{GPIO_SUS5_GPIO_SUS5_PCONF0, GPIO_SUS5_GPIO_SUS5_PAD, 0},
+	{GPIO_SUS6_GPIO_SUS6_PCONF0, GPIO_SUS6_GPIO_SUS6_PAD, 0},
+	{GPIO_SUS7_GPIO_SUS7_PCONF0, GPIO_SUS7_GPIO_SUS7_PAD, 0},
+	{SEC_GPIO_SUS8_GPIO_SUS8_PCONF0, SEC_GPIO_SUS8_GPIO_SUS8_PAD, 0},
+	{SEC_GPIO_SUS9_GPIO_SUS9_PCONF0, SEC_GPIO_SUS9_GPIO_SUS9_PAD, 0},
+	{SEC_GPIO_SUS10_GPIO_SUS10_PCONF0, SEC_GPIO_SUS10_GPIO_SUS10_PAD, 0},
+	{SUSPWRDNACK_GPIOS_11_PCONF0, SUSPWRDNACK_GPIOS_11_PAD, 0},
+	{PMU_SUSCLK_GPIOS_12_PCONF0, PMU_SUSCLK_GPIOS_12_PAD, 0},
+	{PMU_SLP_S0IX_B_GPIOS_13_PCONF0, PMU_SLP_S0IX_B_GPIOS_13_PAD, 0},
+	{PMU_SLP_LAN_B_GPIOS_14_PCONF0, PMU_SLP_LAN_B_GPIOS_14_PAD, 0},
+	{PMU_WAKE_B_GPIOS_15_PCONF0, PMU_WAKE_B_GPIOS_15_PAD, 0},
+	{PMU_PWRBTN_B_GPIOS_16_PCONF0, PMU_PWRBTN_B_GPIOS_16_PAD, 0},
+	{PMU_WAKE_LAN_B_GPIOS_17_PCONF0, PMU_WAKE_LAN_B_GPIOS_17_PAD, 0},
+	{SUS_STAT_B_GPIOS_18_PCONF0, SUS_STAT_B_GPIOS_18_PAD, 0},
+	{USB_OC0_B_GPIOS_19_PCONF0, USB_OC0_B_GPIOS_19_PAD, 0},
+	{USB_OC1_B_GPIOS_20_PCONF0, USB_OC1_B_GPIOS_20_PAD, 0},
+	{SPI_CS1_B_GPIOS_21_PCONF0, SPI_CS1_B_GPIOS_21_PAD, 0},
+	{GPIO_DFX0_GPIOS_22_PCONF0, GPIO_DFX0_GPIOS_22_PAD, 0},
+	{GPIO_DFX1_GPIOS_23_PCONF0, GPIO_DFX1_GPIOS_23_PAD, 0},
+	{GPIO_DFX2_GPIOS_24_PCONF0, GPIO_DFX2_GPIOS_24_PAD, 0},
+	{GPIO_DFX3_GPIOS_25_PCONF0, GPIO_DFX3_GPIOS_25_PAD, 0},
+	{GPIO_DFX4_GPIOS_26_PCONF0, GPIO_DFX4_GPIOS_26_PAD, 0},
+	{GPIO_DFX5_GPIOS_27_PCONF0, GPIO_DFX5_GPIOS_27_PAD, 0},
+	{GPIO_DFX6_GPIOS_28_PCONF0, GPIO_DFX6_GPIOS_28_PAD, 0},
+	{GPIO_DFX7_GPIOS_29_PCONF0, GPIO_DFX7_GPIOS_29_PAD, 0},
+	{GPIO_DFX8_GPIOS_30_PCONF0, GPIO_DFX8_GPIOS_30_PAD, 0},
+	{USB_ULPI_0_CLK_GPIOS_31_PCONF0, USB_ULPI_0_CLK_GPIOS_31_PAD, 0},
+	{USB_ULPI_0_DATA0_GPIOS_32_PCONF0, USB_ULPI_0_DATA0_GPIOS_32_PAD, 0},
+	{USB_ULPI_0_DATA1_GPIOS_33_PCONF0, USB_ULPI_0_DATA1_GPIOS_33_PAD, 0},
+	{USB_ULPI_0_DATA2_GPIOS_34_PCONF0, USB_ULPI_0_DATA2_GPIOS_34_PAD, 0},
+	{USB_ULPI_0_DATA3_GPIOS_35_PCONF0, USB_ULPI_0_DATA3_GPIOS_35_PAD, 0},
+	{USB_ULPI_0_DATA4_GPIOS_36_PCONF0, USB_ULPI_0_DATA4_GPIOS_36_PAD, 0},
+	{USB_ULPI_0_DATA5_GPIOS_37_PCONF0, USB_ULPI_0_DATA5_GPIOS_37_PAD, 0},
+	{USB_ULPI_0_DATA6_GPIOS_38_PCONF0, USB_ULPI_0_DATA6_GPIOS_38_PAD, 0},
+	{USB_ULPI_0_DATA7_GPIOS_39_PCONF0, USB_ULPI_0_DATA7_GPIOS_39_PAD, 0},
+	{USB_ULPI_0_DIR_GPIOS_40_PCONF0, USB_ULPI_0_DIR_GPIOS_40_PAD, 0},
+	{USB_ULPI_0_NXT_GPIOS_41_PCONF0, USB_ULPI_0_NXT_GPIOS_41_PAD, 0},
+	{USB_ULPI_0_STP_GPIOS_42_PCONF0, USB_ULPI_0_STP_GPIOS_42_PAD, 0},
+	{USB_ULPI_0_REFCLK_GPIOS_43_PCONF0, USB_ULPI_0_REFCLK_GPIOS_43_PAD, 0}
 };
 
 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
@@ -259,14 +422,42 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 	u8 gpio, action;
 	u16 function, pad;
 	u32 val;
+	u8 block;
 	struct drm_device *dev = intel_dsi->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
+	DRM_DEBUG_DRIVER("MIPI: executing gpio element\n");
+
+	/*
+	 * Skipping the first byte as it is of no
+	 * interest for android in new version
+	 */
+	if (dev_priv->vbt.dsi.seq_version >= 3)
+		data++;
+
 	gpio = *data++;
 
 	/* pull up/down */
 	action = *data++;
 
+	if (dev_priv->vbt.dsi.seq_version >= 3) {
+		if (gpio <= MAX_GPIO_NUM_NC) {
+			DRM_DEBUG_DRIVER("GPIO is in the north Block\n");
+			block = IOSF_PORT_GPIO_NC;
+		} else if (gpio > MAX_GPIO_NUM_NC && gpio <= MAX_GPIO_NUM_SC) {
+			DRM_DEBUG_DRIVER("GPIO is in the south Block\n");
+			block = IOSF_PORT_GPIO_SC;
+		} else if (gpio > MAX_GPIO_NUM_SC && gpio <= MAX_GPIO_NUM) {
+			DRM_DEBUG_DRIVER("GPIO is in the SUS Block\n");
+			block = IOSF_PORT_GPIO_SUS;
+		} else {
+			DRM_ERROR("GPIO number is not present in the table\n");
+			return NULL;
+		}
+	} else {
+		block = IOSF_PORT_GPIO_NC;
+	}
+
 	function = gtable[gpio].function_reg;
 	pad = gtable[gpio].pad_reg;
 
@@ -274,14 +465,14 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 	if (!gtable[gpio].init) {
 		/* program the function */
 		/* FIXME: remove constant below */
-		vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);
+		vlv_gpio_write(dev_priv, block, function, 0x2000CC00);
 		gtable[gpio].init = 1;
 	}
 
 	val = 0x4 | action;
 
 	/* pull up/down */
-	vlv_gpio_nc_write(dev_priv, pad, val);
+	vlv_gpio_write(dev_priv, block, pad, val);
 	mutex_unlock(&dev_priv->sb_lock);
 
 	return data;
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 8831fc5..3e0cbe6 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -129,17 +129,18 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
 	return val;
 }
 
-u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
+u32 vlv_gpio_read(struct drm_i915_private *dev_priv, u8 core_offset, u32 reg)
 {
 	u32 val = 0;
-	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
+	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), core_offset,
 			SB_CRRDDA_NP, reg, &val);
 	return val;
 }
 
-void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+void vlv_gpio_write(struct drm_i915_private *dev_priv, u8 core_offset,
+				u32 reg, u32 val)
 {
-	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
+	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), core_offset,
 			SB_CRWRDA_NP, reg, &val);
 }
 
-- 
1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[MIPI SEQ PARSING v1 PATCH 6/9] drm/i915: GPIO for CHT generic MIPI

[Deepak M]

From: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>

The GPIO configuration and register offsets are different from
baytrail for cherrytrail. Port the gpio programming accordingly
for cherrytrail in this patch.

Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h            |   23 ++++++
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |  116 +++++++++++++++++++++++-----
 2 files changed, 121 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3efea0e..2d13e34 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -554,11 +554,21 @@
 #define   IOSF_PORT_DPIO			0x12
 #define   IOSF_PORT_DPIO_2			0x1a
 #define   IOSF_PORT_GPIO_NC			0x13
+#define   CHV_IOSF_PORT_GPIO_N			0x13
 #define   IOSF_PORT_GPIO_SC			0x48
+#define   CHV_IOSF_PORT_GPIO_SE			0x48
+#define   CHV_IOSF_PORT_GPIO_SW			0xB2
 #define   IOSF_PORT_GPIO_SUS			0xA8
+#define   CHV_IOSF_PORT_GPIO_E			0xA8
 #define   MAX_GPIO_NUM_NC			26
 #define   MAX_GPIO_NUM_SC			128
 #define   MAX_GPIO_NUM				172
+#define   CHV_MAX_GPIO_NUM_N			72
+#define   CHV_MAX_GPIO_NUM_SE			99
+#define   CHV_MAX_GPIO_NUM_SW			197
+#define   CHV_MIN_GPIO_NUM_SE			73
+#define   CHV_MIN_GPIO_NUM_SW			100
+#define   CHV_MIN_GPIO_NUM_E			198
 #define   IOSF_PORT_CCK				0x14
 #define   IOSF_PORT_CCU				0xA9
 #define   IOSF_PORT_GPS_CORE			0x48
@@ -566,6 +576,19 @@
 #define VLV_IOSF_DATA				(VLV_DISPLAY_BASE + 0x2104)
 #define VLV_IOSF_ADDR				(VLV_DISPLAY_BASE + 0x2108)
 
+#define VLV_GPIO_CFG				0x2000CC00
+#define VLV_GPIO_INPUT_DIS			0x04
+
+#define CHV_PAD_FMLY_BASE			0x4400
+#define CHV_PAD_FMLY_SIZE			0x400
+#define CHV_PAD_CFG_0_1_REG_SIZE		0x8
+#define CHV_PAD_CFG_REG_SIZE			0x4
+#define CHV_VBT_MAX_PINS_PER_FMLY		15
+
+#define CHV_GPIO_CFG_UNLOCK			0x00000000
+#define CHV_GPIO_CFG_HiZ			0x00008100
+#define CHV_GPIO_CFG_TX_STATE_SHIFT		1
+
 /* See configdb bunit SB addr map */
 #define BUNIT_REG_BISOC				0x11
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index f2ea875..060305d 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -416,17 +416,75 @@ static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
 
 	return data;
 }
-
-static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
+static int chv_program_gpio(struct intel_dsi *intel_dsi,
+				const u8 *data, const u8 **cur_data)
 {
+	struct drm_device *dev = intel_dsi->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	u8 gpio, action;
+	u16 family_num;
 	u16 function, pad;
-	u32 val;
 	u8 block;
+
+	/*
+	 * Skipping the first byte as it is of no
+	 * interest for linux kernel in new VBT version
+	 */
+	if (dev_priv->vbt.dsi.seq_version >= 3)
+		data++;
+
+	gpio = *data++;
+
+	/* pull up/down */
+	action = *data++;
+
+	if (dev_priv->vbt.dsi.seq_version >= 3) {
+		if (gpio <= CHV_MAX_GPIO_NUM_N) {
+			block = CHV_IOSF_PORT_GPIO_N;
+			DRM_DEBUG_DRIVER("GPIO is in the north Block\n");
+		} else if (gpio <= CHV_MAX_GPIO_NUM_SE) {
+			block = CHV_IOSF_PORT_GPIO_SE;
+			gpio = gpio - CHV_MIN_GPIO_NUM_SE;
+			DRM_DEBUG_DRIVER("GPIO is in the south east Block\n");
+		} else if (gpio <= CHV_MAX_GPIO_NUM_SW) {
+			block = CHV_IOSF_PORT_GPIO_SW;
+			gpio = gpio - CHV_MIN_GPIO_NUM_SW;
+			DRM_DEBUG_DRIVER("GPIO is in the south west Block\n");
+		} else {
+			block = CHV_IOSF_PORT_GPIO_E;
+			gpio = gpio - CHV_MIN_GPIO_NUM_E;
+			DRM_DEBUG_DRIVER("GPIO is in the east Block\n");
+		}
+	} else
+		block = IOSF_PORT_GPIO_NC;
+
+	family_num =  gpio / CHV_VBT_MAX_PINS_PER_FMLY;
+	gpio = gpio - (family_num * CHV_VBT_MAX_PINS_PER_FMLY);
+	pad = CHV_PAD_FMLY_BASE + (family_num * CHV_PAD_FMLY_SIZE) +
+			(((u16)gpio) * CHV_PAD_CFG_0_1_REG_SIZE);
+	function = pad + CHV_PAD_CFG_REG_SIZE;
+
+	mutex_lock(&dev_priv->sb_lock);
+	vlv_gpio_write(dev_priv, block, function,
+					CHV_GPIO_CFG_UNLOCK);
+	vlv_gpio_write(dev_priv, block, pad, CHV_GPIO_CFG_HiZ |
+			(action << CHV_GPIO_CFG_TX_STATE_SHIFT));
+	mutex_unlock(&dev_priv->sb_lock);
+
+	*cur_data = data;
+
+	return 0;
+}
+
+static int vlv_program_gpio(struct intel_dsi *intel_dsi,
+				const u8 *data, const u8 **cur_data)
+{
 	struct drm_device *dev = intel_dsi->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	DRM_DEBUG_DRIVER("MIPI: executing gpio element\n");
+	u8 gpio, action;
+	u16 function, pad;
+	u32 val;
+	u8 block;
 
 	/*
 	 * Skipping the first byte as it is of no
@@ -442,42 +500,64 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 
 	if (dev_priv->vbt.dsi.seq_version >= 3) {
 		if (gpio <= MAX_GPIO_NUM_NC) {
-			DRM_DEBUG_DRIVER("GPIO is in the north Block\n");
 			block = IOSF_PORT_GPIO_NC;
+			DRM_DEBUG_DRIVER("GPIO is in the north Block\n");
 		} else if (gpio > MAX_GPIO_NUM_NC && gpio <= MAX_GPIO_NUM_SC) {
-			DRM_DEBUG_DRIVER("GPIO is in the south Block\n");
 			block = IOSF_PORT_GPIO_SC;
+			DRM_DEBUG_DRIVER("GPIO is in the south Block\n");
 		} else if (gpio > MAX_GPIO_NUM_SC && gpio <= MAX_GPIO_NUM) {
-			DRM_DEBUG_DRIVER("GPIO is in the SUS Block\n");
 			block = IOSF_PORT_GPIO_SUS;
+			DRM_DEBUG_DRIVER("GPIO is in the SUS Block\n");
 		} else {
 			DRM_ERROR("GPIO number is not present in the table\n");
-			return NULL;
+			return -EINVAL;
 		}
-	} else {
+	} else
 		block = IOSF_PORT_GPIO_NC;
-	}
 
 	function = gtable[gpio].function_reg;
 	pad = gtable[gpio].pad_reg;
 
 	mutex_lock(&dev_priv->sb_lock);
+
 	if (!gtable[gpio].init) {
-		/* program the function */
-		/* FIXME: remove constant below */
-		vlv_gpio_write(dev_priv, block, function, 0x2000CC00);
-		gtable[gpio].init = 1;
+		vlv_gpio_write(dev_priv, block, function,
+						VLV_GPIO_CFG);
+		gtable[gpio].init = true;
 	}
-
-	val = 0x4 | action;
+	val = VLV_GPIO_INPUT_DIS | action;
 
 	/* pull up/down */
 	vlv_gpio_write(dev_priv, block, pad, val);
+
 	mutex_unlock(&dev_priv->sb_lock);
 
-	return data;
+	*cur_data = data;
+
+	return 0;
 }
 
+static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
+{
+	struct drm_device *dev = intel_dsi->base.base.dev;
+	int ret;
+
+	DRM_DEBUG_DRIVER("MIPI: executing gpio element\n");
+
+	ret = -EINVAL;
+
+	if (IS_CHERRYVIEW(dev))
+		ret = chv_program_gpio(intel_dsi, data, &data);
+	else if (IS_VALLEYVIEW(dev))
+		ret = vlv_program_gpio(intel_dsi, data, &data);
+	else
+		DRM_ERROR("GPIO programming missing for this platform.\n");
+
+	if (ret)
+		return NULL;
+
+	return data;
+}
 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
 					const u8 *data);
 static const fn_mipi_elem_exec exec_elem[] = {
-- 
1.7.9.5

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[MIPI SEQ PARSING v1 PATCH 7/9] drm: Add few more wrapper functions for drm panel

[Deepak M]

Currently there are few pair of functions which
are called during the panel enable/disable sequence.
To improve the granularity, adding few more wrapper
functions so that the functions are more specific
on what they are doing and also in some cases
some specific operations have to be done between these
functions.

Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 include/drm/drm_panel.h |   47 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
index 13ff44b..c729f6d 100644
--- a/include/drm/drm_panel.h
+++ b/include/drm/drm_panel.h
@@ -73,6 +73,12 @@ struct drm_panel_funcs {
 	int (*get_modes)(struct drm_panel *panel);
 	int (*get_timings)(struct drm_panel *panel, unsigned int num_timings,
 			   struct display_timing *timings);
+	int (*power_on)(struct drm_panel *panel);
+	int (*power_off)(struct drm_panel *panel);
+	int (*backlight_on)(struct drm_panel *panel);
+	int (*backlight_off)(struct drm_panel *panel);
+	int (*get_info)(struct drm_panel *panel,
+				struct drm_connector *connector);
 };
 
 struct drm_panel {
@@ -117,6 +123,47 @@ static inline int drm_panel_enable(struct drm_panel *panel)
 	return panel ? -ENOSYS : -EINVAL;
 }
 
+static inline int drm_panel_power_on(struct drm_panel *panel)
+{
+	if (panel && panel->funcs && panel->funcs->power_on)
+		return panel->funcs->power_on(panel);
+
+	return panel ? -ENOSYS : -EINVAL;
+}
+
+static inline int drm_panel_power_off(struct drm_panel *panel)
+{
+	if (panel && panel->funcs && panel->funcs->power_off)
+		return panel->funcs->power_off(panel);
+
+	return panel ? -ENOSYS : -EINVAL;
+}
+
+static inline int drm_panel_backlight_on(struct drm_panel *panel)
+{
+	if (panel && panel->funcs && panel->funcs->backlight_on)
+		return panel->funcs->backlight_on(panel);
+
+	return panel ? -ENOSYS : -EINVAL;
+}
+
+static inline int drm_panel_backlight_off(struct drm_panel *panel)
+{
+	if (panel && panel->funcs && panel->funcs->backlight_off)
+		return panel->funcs->backlight_off(panel);
+
+	return panel ? -ENOSYS : -EINVAL;
+}
+
+static inline int drm_panel_get_info(struct drm_panel *panel,
+				struct drm_connector *connector)
+{
+	if (connector && panel && panel->funcs && panel->funcs->get_info)
+		return panel->funcs->get_info(panel, connector);
+
+	return panel ? -ENOSYS : -EINVAL;
+}
+
 static inline int drm_panel_get_modes(struct drm_panel *panel)
 {
 	if (panel && panel->funcs && panel->funcs->get_modes)
-- 
1.7.9.5

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[MIPI SEQ PARSING v1 PATCH 8/9] drm/i915: Add functions to execute the new sequences from VBT

[Deepak M]

From: Gaurav K Singh <gaurav.k.singh@intel.com>

New sequences are added in the mipi sequence block of the
VBT from version 3 onwards. The sequences are added to
make the code more generic as the panel related info
are placed in the VBT.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Deepak M <m.deepak@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   84 +++++++++++++++++++++++++++-
 1 file changed, 83 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 060305d..c6f66e4 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -581,7 +581,13 @@ static const char * const seq_name[] = {
 	"MIPI_SEQ_INIT_OTP",
 	"MIPI_SEQ_DISPLAY_ON",
 	"MIPI_SEQ_DISPLAY_OFF",
-	"MIPI_SEQ_DEASSERT_RESET"
+	"MIPI_SEQ_DEASSERT_RESET",
+	"MIPI_SEQ_BACKLIGHT_ON",
+	"MIPI_SEQ_BACKLIGHT_OFF",
+	"MIPI_SEQ_TEAR_ON",
+	"MIPI_SEQ_TEAR_OFF",
+	"MIPI_SEQ_POWER_ON",
+	"MIPI_SEQ_POWER_OFF"
 };
 
 static void generic_exec_sequence(struct intel_dsi *intel_dsi, const u8 *data)
@@ -710,12 +716,88 @@ static int vbt_panel_get_modes(struct drm_panel *panel)
 	return 1;
 }
 
+static int vbt_panel_power_on(struct drm_panel *panel)
+{
+	struct vbt_panel *vbt_panel = to_vbt_panel(panel);
+	struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
+	struct drm_device *dev = intel_dsi->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	const u8 *sequence;
+
+	sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_POWER_ON];
+	generic_exec_sequence(intel_dsi, sequence);
+
+	return 0;
+}
+
+static int vbt_panel_power_off(struct drm_panel *panel)
+{
+	struct vbt_panel *vbt_panel = to_vbt_panel(panel);
+	struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
+	struct drm_device *dev = intel_dsi->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	const u8 *sequence;
+
+	sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_POWER_OFF];
+	generic_exec_sequence(intel_dsi, sequence);
+
+	return 0;
+}
+
+static int vbt_panel_backlight_on(struct drm_panel *panel)
+{
+	struct vbt_panel *vbt_panel = to_vbt_panel(panel);
+	struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
+	struct drm_device *dev = intel_dsi->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	const u8 *sequence;
+
+	sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_BACKLIGHT_ON];
+	generic_exec_sequence(intel_dsi, sequence);
+
+	return 0;
+}
+
+static int vbt_panel_backlight_off(struct drm_panel *panel)
+{
+	struct vbt_panel *vbt_panel = to_vbt_panel(panel);
+	struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
+	struct drm_device *dev = intel_dsi->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	const u8 *sequence;
+
+	sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_BACKLIGHT_OFF];
+	generic_exec_sequence(intel_dsi, sequence);
+
+	return 0;
+}
+
+static int vbt_panel_get_info(struct drm_panel *panel,
+					struct drm_connector *connector)
+{
+	struct intel_connector *intel_connector =
+				to_intel_connector(connector);
+
+	if (intel_connector) {
+		connector->display_info.width_mm =
+				intel_connector->panel.fixed_mode->width_mm;
+		connector->display_info.height_mm =
+				intel_connector->panel.fixed_mode->height_mm;
+	}
+	return 0;
+}
+
 static const struct drm_panel_funcs vbt_panel_funcs = {
 	.disable = vbt_panel_disable,
 	.unprepare = vbt_panel_unprepare,
 	.prepare = vbt_panel_prepare,
 	.enable = vbt_panel_enable,
 	.get_modes = vbt_panel_get_modes,
+	.power_on = vbt_panel_power_on,
+	.power_off = vbt_panel_power_off,
+	.backlight_on = vbt_panel_backlight_on,
+	.backlight_off = vbt_panel_backlight_off,
+	.get_info = vbt_panel_get_info,
 };
 
 struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
-- 
1.7.9.5

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[MIPI SEQ PARSING v1 PATCH 9/9] BXT GPIO support for backlight and panel control

[Deepak M]

From: Uma Shankar <uma.shankar@intel.com>

Added the BXT GPIO pin configuration and programming logic for
backlight and panel control.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   46 ++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index c6f66e4..f27a568 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -32,6 +32,7 @@
 #include <linux/slab.h>
 #include <video/mipi_display.h>
 #include <linux/i2c.h>
+#include <linux/gpio.h>
 #include <asm/intel-mid.h>
 #include <video/mipi_display.h>
 #include "i915_drv.h"
@@ -325,6 +326,16 @@ out:
 	return data;
 }
 
+struct bxt_gpio_table {
+	u16 gpio_pin;
+	u16 offset;
+};
+
+static struct bxt_gpio_table bxt_gtable[] = {
+	{0xC1, 270},
+	{0x1B, 456}
+};
+
 static inline enum port intel_dsi_seq_port_to_port(u8 port)
 {
 	return port ? PORT_C : PORT_A;
@@ -537,6 +548,39 @@ static int vlv_program_gpio(struct intel_dsi *intel_dsi,
 	return 0;
 }
 
+static int bxt_program_gpio(struct intel_dsi *intel_dsi,
+				const u8 *data, const u8 **cur_data)
+{
+	struct drm_device *dev = intel_dsi->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u8 gpio, action;
+	u16 function;
+
+	/*
+	 * Skipping the first byte as it is of no
+	 * interest for android in new version
+	 */
+	if (dev_priv->vbt.dsi.seq_version >= 3)
+		data++;
+
+	gpio = *data++;
+
+	/* pull up/down */
+	action = *data++;
+	function = (bxt_gtable[0].gpio_pin == gpio) ?
+		bxt_gtable[0].offset :
+		(bxt_gtable[1].gpio_pin == gpio) ?
+		bxt_gtable[1].offset : 0;
+	if (!function)
+		return -1;
+
+	gpio_request_one(function, GPIOF_DIR_OUT, "MIPI");
+	gpio_set_value(function, action);
+
+	*cur_data = data;
+	return 0;
+}
+
 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 {
 	struct drm_device *dev = intel_dsi->base.base.dev;
@@ -550,6 +594,8 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 		ret = chv_program_gpio(intel_dsi, data, &data);
 	else if (IS_VALLEYVIEW(dev))
 		ret = vlv_program_gpio(intel_dsi, data, &data);
+	else if (IS_BROXTON(dev))
+		ret = bxt_program_gpio(intel_dsi, data, &data);
 	else
 		DRM_ERROR("GPIO programming missing for this platform.\n");
 
-- 
1.7.9.5

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Re: [MIPI SEQ PARSING v1 PATCH 2/9] drm/i915: Parsing VBT if size of VBT exceeds 6KB

[Jani Nikula]

On Tue, 28 Jul 2015, Deepak M <m.deepak@intel.com> wrote:
> Currently the iomap for VBT works only if the size of the
> VBT is less than 6KB, but if the size of the VBT exceeds
> 6KB than the physical address and the size of the VBT to
> be iomapped is specified in the mailbox3 and is iomapped
> accordingly.
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_bios.c     |   13 +++++++----
>  drivers/gpu/drm/i915/intel_opregion.c |   39 ++++++++++++++++++++++++++++++---
>  2 files changed, 45 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 2583587..1b9164e 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -1219,6 +1219,7 @@ intel_parse_bios(struct drm_device *dev)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct pci_dev *pdev = dev->pdev;
>  	const struct bdb_header *bdb = NULL;
> +	const struct vbt_header *vbt = NULL;
>  	u8 __iomem *bios = NULL;
>  
>  	if (HAS_PCH_NOP(dev))
> @@ -1226,10 +1227,14 @@ intel_parse_bios(struct drm_device *dev)
>  
>  	init_vbt_defaults(dev_priv);
>  
> -	/* XXX Should this validation be moved to intel_opregion.c? */
> -	if (!dmi_check_system(intel_no_opregion_vbt) && dev_priv->opregion.vbt)
> -		bdb = validate_vbt(dev_priv->opregion.header, OPREGION_SIZE,
> -				   dev_priv->opregion.vbt, "OpRegion");
> +	if (!dmi_check_system(intel_no_opregion_vbt) &&
> +			dev_priv->opregion.vbt) {
> +		vbt = (struct vbt_header *)dev_priv->opregion.vbt;
> +		bdb = (struct bdb_header *)(dev_priv->opregion.vbt +
> +				vbt->bdb_offset);
> +		DRM_DEBUG_KMS("Using VBT from Opregion: %20s\n",
> +				vbt->signature);
> +	}

Please read the comment in the beginning of validate_vbt. Please keep
things that way. I put in some effort to clean this up and get rid of a
bunch of extra casts, so please don't add new ones back.

You should probably move some of this stuff to intel_opregion.c and have
a function to return the struct bdb_header *pointer from there.

Please also look into in i915_opregion in i915_debugfs.c, and fix that.

>  
>  	if (bdb == NULL) {
>  		size_t size;
> diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
> index 71e87ab..1372e39 100644
> --- a/drivers/gpu/drm/i915/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/intel_opregion.c
> @@ -50,6 +50,7 @@
>  #define OPREGION_VBT_OFFSET    0x400
>  
>  #define OPREGION_SIGNATURE "IntelGraphicsMem"
> +#define VBT_SIGNATURE	"$VBT"

Adding this does you no good when you're duplicating this from
intel_bios.c and not removing any from there... really the check should
be in one place only.

>  #define MBOX_ACPI      (1<<0)
>  #define MBOX_SWSCI     (1<<1)
>  #define MBOX_ASLE      (1<<2)
> @@ -113,7 +114,12 @@ struct opregion_asle {
>  	u32 pcft;       /* power conservation features */
>  	u32 srot;       /* supported rotation angles */
>  	u32 iuer;       /* IUER events */
> -	u8 rsvd[86];
> +	u64 fdss;	/* DSS Buffer address allocated for IFFS feature */
> +	u32 fdsp;	/* Size of DSS Buffer */
> +	u32 stat;	/* State Indicator */
> +	u64 rvda;	/* Physical address of raw vbt data */
> +	u32 rvds;	/* Size of raw vbt data */
> +	u8 rsvd[58];

These should be a prep patch that could be merged quickly with a check
against the spec.

>  } __packed;
>  
>  /* Driver readiness indicator */
> @@ -858,8 +864,10 @@ int intel_opregion_setup(struct drm_device *dev)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_opregion *opregion = &dev_priv->opregion;
>  	void __iomem *base;
> +	void __iomem *vbt_base;
>  	u32 asls, mboxes;
>  	char buf[sizeof(OPREGION_SIGNATURE)];
> +	char vbt_sig_buf[sizeof(VBT_SIGNATURE)];
>  	int err = 0;
>  
>  	pci_read_config_dword(dev->pdev, PCI_ASLS, &asls);
> @@ -873,7 +881,7 @@ int intel_opregion_setup(struct drm_device *dev)
>  	INIT_WORK(&opregion->asle_work, asle_work);
>  #endif
>  
> -	base = acpi_os_ioremap(asls, OPREGION_SIZE);
> +	base = acpi_os_ioremap(asls, OPREGION_VBT_OFFSET);
>  	if (!base)
>  		return -ENOMEM;
>  
> @@ -884,8 +892,31 @@ int intel_opregion_setup(struct drm_device *dev)
>  		err = -EINVAL;
>  		goto err_out;
>  	}
> +
>  	opregion->header = base;
> -	opregion->vbt = base + OPREGION_VBT_OFFSET;
> +	opregion->asle = base + OPREGION_ASLE_OFFSET;

Why is this addition needed or even correct?

> +
> +	if (opregion->header->opregion_ver >= 2) {
> +		if (opregion->asle->rvda)
> +			vbt_base = acpi_os_ioremap(opregion->asle->rvda,
> +						opregion->asle->rvds);
> +		else
> +			vbt_base = acpi_os_ioremap(asls + OPREGION_VBT_OFFSET,
> +					OPREGION_SIZE - OPREGION_VBT_OFFSET);
> +	} else
> +		vbt_base = acpi_os_ioremap(asls + OPREGION_VBT_OFFSET,
> +					OPREGION_SIZE - OPREGION_VBT_OFFSET);

The two else branches are identical.

> +
> +
> +	memcpy_fromio(vbt_sig_buf, vbt_base, sizeof(vbt_sig_buf));

This is silly, just do what validate_vbt does. (I know, there's
silliness for the opregion signature there already.)

> +
> +	if (memcmp(vbt_sig_buf, VBT_SIGNATURE, 4)) {
> +		DRM_ERROR("VBT signature mismatch\n");
> +		err = -EINVAL;
> +		goto err_vbt;
> +	}
> +
> +	opregion->vbt = vbt_base;
>  
>  	opregion->lid_state = base + ACPI_CLID;
>  
> @@ -909,6 +940,8 @@ int intel_opregion_setup(struct drm_device *dev)
>  
>  	return 0;
>  
> +err_vbt:
> +	iounmap(vbt_base);
>  err_out:
>  	iounmap(base);
>  	return err;
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [MIPI SEQ PARSING v1 PATCH 3/9] drm/i915: Using the approprite vbt size if vbt is not in mailbox4 of opregion

[Jani Nikula]

On Tue, 28 Jul 2015, Deepak M <m.deepak@intel.com> wrote:
> Currently the field in bdb header which indicates the VBT size
> is of 2 bytes, but there are some cases where VBT size exceeds
> 64KB in which case this field may not contain the correct VBT size.
> So its better to get the VBT size from the mailbox3 if
> VBT is not present in the mailbox4 of opregion.
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h       |    5 ++++
>  drivers/gpu/drm/i915/intel_bios.c     |   43 +++++++++++++++++++--------------
>  drivers/gpu/drm/i915/intel_opregion.c |    7 ++++--
>  3 files changed, 35 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1dbd957..b38f52ee 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1740,6 +1740,11 @@ struct drm_i915_private {
>  	u32 pm_rps_events;
>  	u32 pipestat_irq_mask[I915_MAX_PIPES];
>  
> +	bool vbt_in_mailbox4;
> +
> +	/* value is true when VBT is present in mailbox4 */
> +	u32 vbt_size;
> +

There's already struct intel_opregion opregion field in dev_priv where
this belongs instead of cluttering the top level.

You should only add vbt size in the struct, and make sure it's valid for
all scenarios, mailbox 4 or not, and always check against that. Having
size fields with separate validity fields will drive people insane.

>  	struct i915_hotplug hotplug;
>  	struct i915_fbc fbc;
>  	struct i915_drrs drrs;
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 1b9164e..5e0ff22 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -37,17 +37,22 @@
>  static int panel_type;
>  
>  static const void *
> -find_section(const void *_bdb, int section_id)
> +find_section(struct drm_i915_private *dev_priv,
> +		const void *_bdb, int section_id)
>  {
>  	const struct bdb_header *bdb = _bdb;
>  	const u8 *base = _bdb;
>  	int index = 0;
> -	u16 total, current_size;
> +	u32 total, current_size;
>  	u8 current_id;
>  
>  	/* skip to first section */
>  	index += bdb->header_size;
> -	total = bdb->bdb_size;
> +
> +	if (dev_priv->vbt_in_mailbox4)
> +		total = bdb->bdb_size;
> +	else
> +		total = dev_priv->vbt_size;
>  
>  	/* walk the sections looking for section_id */
>  	while (index + 3 < total) {
> @@ -179,7 +184,7 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
>  	struct drm_display_mode *panel_fixed_mode;
>  	int drrs_mode;
>  
> -	lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
> +	lvds_options = find_section(dev_priv, bdb, BDB_LVDS_OPTIONS);
>  	if (!lvds_options)
>  		return;
>  
> @@ -211,11 +216,12 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
>  		break;
>  	}
>  
> -	lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
> +	lvds_lfp_data = find_section(dev_priv, bdb, BDB_LVDS_LFP_DATA);
>  	if (!lvds_lfp_data)
>  		return;
>  
> -	lvds_lfp_data_ptrs = find_section(bdb, BDB_LVDS_LFP_DATA_PTRS);
> +	lvds_lfp_data_ptrs = find_section(dev_priv, bdb,
> +					BDB_LVDS_LFP_DATA_PTRS);
>  	if (!lvds_lfp_data_ptrs)
>  		return;
>  
> @@ -257,7 +263,7 @@ parse_lfp_backlight(struct drm_i915_private *dev_priv,
>  	const struct bdb_lfp_backlight_data *backlight_data;
>  	const struct bdb_lfp_backlight_data_entry *entry;
>  
> -	backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT);
> +	backlight_data = find_section(dev_priv, bdb, BDB_LVDS_BACKLIGHT);
>  	if (!backlight_data)
>  		return;
>  
> @@ -305,14 +311,15 @@ parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
>  	if (index == -1) {
>  		const struct bdb_sdvo_lvds_options *sdvo_lvds_options;
>  
> -		sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS);
> +		sdvo_lvds_options = find_section(dev_priv, bdb,
> +						BDB_SDVO_LVDS_OPTIONS);
>  		if (!sdvo_lvds_options)
>  			return;
>  
>  		index = sdvo_lvds_options->panel_type;
>  	}
>  
> -	dvo_timing = find_section(bdb, BDB_SDVO_PANEL_DTDS);
> +	dvo_timing = find_section(dev_priv, bdb, BDB_SDVO_PANEL_DTDS);
>  	if (!dvo_timing)
>  		return;
>  
> @@ -349,7 +356,7 @@ parse_general_features(struct drm_i915_private *dev_priv,
>  	struct drm_device *dev = dev_priv->dev;
>  	const struct bdb_general_features *general;
>  
> -	general = find_section(bdb, BDB_GENERAL_FEATURES);
> +	general = find_section(dev_priv, bdb, BDB_GENERAL_FEATURES);
>  	if (general) {
>  		dev_priv->vbt.int_tv_support = general->int_tv_support;
>  		dev_priv->vbt.int_crt_support = general->int_crt_support;
> @@ -374,7 +381,7 @@ parse_general_definitions(struct drm_i915_private *dev_priv,
>  {
>  	const struct bdb_general_definitions *general;
>  
> -	general = find_section(bdb, BDB_GENERAL_DEFINITIONS);
> +	general = find_section(dev_priv, bdb, BDB_GENERAL_DEFINITIONS);
>  	if (general) {
>  		u16 block_size = get_blocksize(general);
>  		if (block_size >= sizeof(*general)) {
> @@ -405,7 +412,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
>  	int i, child_device_num, count;
>  	u16	block_size;
>  
> -	p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
> +	p_defs = find_section(dev_priv, bdb, BDB_GENERAL_DEFINITIONS);
>  	if (!p_defs) {
>  		DRM_DEBUG_KMS("No general definition block is found, unable to construct sdvo mapping.\n");
>  		return;
> @@ -491,7 +498,7 @@ parse_driver_features(struct drm_i915_private *dev_priv,
>  {
>  	const struct bdb_driver_features *driver;
>  
> -	driver = find_section(bdb, BDB_DRIVER_FEATURES);
> +	driver = find_section(dev_priv, bdb, BDB_DRIVER_FEATURES);
>  	if (!driver)
>  		return;
>  
> @@ -519,7 +526,7 @@ parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
>  	const struct edp_power_seq *edp_pps;
>  	const struct edp_link_params *edp_link_params;
>  
> -	edp = find_section(bdb, BDB_EDP);
> +	edp = find_section(dev_priv, bdb, BDB_EDP);
>  	if (!edp) {
>  		if (dev_priv->vbt.edp_support)
>  			DRM_DEBUG_KMS("No eDP BDB found but eDP panel supported.\n");
> @@ -630,7 +637,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
>  	const struct bdb_psr *psr;
>  	const struct psr_table *psr_table;
>  
> -	psr = find_section(bdb, BDB_PSR);
> +	psr = find_section(dev_priv, bdb, BDB_PSR);
>  	if (!psr) {
>  		DRM_DEBUG_KMS("No PSR BDB found.\n");
>  		return;
> @@ -768,7 +775,7 @@ parse_mipi(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
>  	/* Parse #52 for panel index used from panel_type already
>  	 * parsed
>  	 */
> -	start = find_section(bdb, BDB_MIPI_CONFIG);
> +	start = find_section(dev_priv, bdb, BDB_MIPI_CONFIG);
>  	if (!start) {
>  		DRM_DEBUG_KMS("No MIPI config BDB found");
>  		return;
> @@ -799,7 +806,7 @@ parse_mipi(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
>  	dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
>  
>  	/* Check if we have sequence block as well */
> -	sequence = find_section(bdb, BDB_MIPI_SEQUENCE);
> +	sequence = find_section(dev_priv, bdb, BDB_MIPI_SEQUENCE);
>  	if (!sequence) {
>  		DRM_DEBUG_KMS("No MIPI Sequence found, parsing complete\n");
>  		return;
> @@ -1023,7 +1030,7 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
>  	int i, child_device_num, count;
>  	u16	block_size;
>  
> -	p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
> +	p_defs = find_section(dev_priv, bdb, BDB_GENERAL_DEFINITIONS);
>  	if (!p_defs) {
>  		DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n");
>  		return;
> diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
> index 1372e39..1f76715 100644
> --- a/drivers/gpu/drm/i915/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/intel_opregion.c
> @@ -896,11 +896,14 @@ int intel_opregion_setup(struct drm_device *dev)
>  	opregion->header = base;
>  	opregion->asle = base + OPREGION_ASLE_OFFSET;
>  
> +	dev_priv->vbt_in_mailbox4 = true;
>  	if (opregion->header->opregion_ver >= 2) {
> -		if (opregion->asle->rvda)
> +		if (opregion->asle->rvda) {
>  			vbt_base = acpi_os_ioremap(opregion->asle->rvda,
>  						opregion->asle->rvds);
> -		else
> +			dev_priv->vbt_in_mailbox4 = false;
> +			dev_priv->vbt_size = opregion->asle->rvds;
> +		} else
>  			vbt_base = acpi_os_ioremap(asls + OPREGION_VBT_OFFSET,
>  					OPREGION_SIZE - OPREGION_VBT_OFFSET);
>  	} else
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [MIPI SEQ PARSING v1 PATCH 1/9] drm/i915: Adding the parsing logic for the i2c element

[Jani Nikula]

On Tue, 28 Jul 2015, Deepak M <m.deepak@intel.com> wrote:
> From: vkorjani <vikas.korjani@intel.com>
>
> New sequence element for i2c is been added in the
> mipi sequence block of the VBT. This patch parses
> and executes the i2c sequence.
>
> Signed-off-by: vkorjani <vikas.korjani@intel.com>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_bios.c          |    6 +++
>  drivers/gpu/drm/i915/intel_bios.h          |    1 +
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   59 ++++++++++++++++++++++++++++
>  3 files changed, 66 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 2ff9eb0..2583587 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -714,6 +714,12 @@ static u8 *goto_next_sequence(u8 *data, int *size)
>  
>  			data += 3;
>  			break;
> +		case MIPI_SEQ_ELEM_I2C:
> +			/* skip by this element payload size */
> +			data += 7;
> +			len = *data;
> +			data += len + 1;
> +			break;
>  		default:
>  			DRM_ERROR("Unknown element\n");
>  			return NULL;
> diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
> index af0b476..1703a83 100644
> --- a/drivers/gpu/drm/i915/intel_bios.h
> +++ b/drivers/gpu/drm/i915/intel_bios.h
> @@ -942,6 +942,7 @@ enum mipi_seq_element {
>  	MIPI_SEQ_ELEM_SEND_PKT,
>  	MIPI_SEQ_ELEM_DELAY,
>  	MIPI_SEQ_ELEM_GPIO,
> +	MIPI_SEQ_ELEM_I2C,
>  	MIPI_SEQ_ELEM_STATUS,
>  	MIPI_SEQ_ELEM_MAX
>  };
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index a5e99ac..e061a42 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -31,6 +31,7 @@
>  #include <drm/drm_panel.h>
>  #include <linux/slab.h>
>  #include <video/mipi_display.h>
> +#include <linux/i2c.h>
>  #include <asm/intel-mid.h>
>  #include <video/mipi_display.h>
>  #include "i915_drv.h"
> @@ -104,6 +105,63 @@ static struct gpio_table gtable[] = {
>  	{ GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
>  };
>  
> +static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
> +{
> +	struct i2c_adapter *adapter;
> +	int ret;
> +	u8 reg_offset, payload_size, retries = 5;
> +	struct i2c_msg msg;
> +	u8 *transmit_buffer = NULL;
> +	u8 flag = *data++;
> +	u8 index = *data++;
> +	u8 bus_number = *data++;
> +	u16 slave_add = *(u16 *)(data);
> +
> +	data = data + 2;
> +	reg_offset = *data++;
> +	payload_size = *data++;
> +
> +	adapter = i2c_get_adapter(bus_number);

Where's the corresponding i2c_put_adapter?

BR,
Jani.

> +
> +	if (!adapter) {
> +		DRM_ERROR("i2c_get_adapter(%u) failed, index:%u flag: %u\n",
> +				(bus_number + 1), index, flag);
> +		goto out;
> +	}
> +
> +	transmit_buffer = kmalloc(1 + payload_size, GFP_TEMPORARY);
> +
> +	if (!transmit_buffer)
> +		goto out;
> +
> +	transmit_buffer[0] = reg_offset;
> +	memcpy(&transmit_buffer[1], data, (size_t)payload_size);
> +
> +	msg.addr   = slave_add;
> +	msg.flags  = 0;
> +	msg.len    = 2;
> +	msg.buf    = &transmit_buffer[0];
> +
> +	do {
> +		ret =  i2c_transfer(adapter, &msg, 1);
> +		if (ret == -EAGAIN)
> +			usleep_range(1000, 2500);
> +		else if (ret != 1) {
> +			DRM_ERROR("i2c transfer failed %d\n", ret);
> +			break;
> +		}
> +	} while (retries--);
> +
> +	if (retries == 0)
> +		DRM_ERROR("i2c transfer failed");
> +
> +out:
> +	kfree(transmit_buffer);
> +
> +	data = data + payload_size;
> +	return data;
> +}
> +
>  static inline enum port intel_dsi_seq_port_to_port(u8 port)
>  {
>  	return port ? PORT_C : PORT_A;
> @@ -236,6 +294,7 @@ static const fn_mipi_elem_exec exec_elem[] = {
>  	mipi_exec_send_packet,
>  	mipi_exec_delay,
>  	mipi_exec_gpio,
> +	mipi_exec_i2c,
>  	NULL, /* status read; later */
>  };
>  
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [MIPI SEQ PARSING v1 PATCH 5/9] drm/i915: Added the generic gpio sequence support and gpio table

[Jani Nikula]

On Tue, 28 Jul 2015, Deepak M <m.deepak@intel.com> wrote:
> The generic gpio is sequence is parsed from the VBT and the
> GPIO table is updated with the North core, South core and
> SUS core elements.
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h            |    5 +-
>  drivers/gpu/drm/i915/i915_reg.h            |    5 +
>  drivers/gpu/drm/i915/intel_dsi.h           |  355 ++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |  219 +++++++++++++++--
>  drivers/gpu/drm/i915/intel_sideband.c      |    9 +-

The changes to intel_sideband.c should be a separate patch.

BR,
Jani.

>  5 files changed, 573 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b38f52ee..8cf133e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3306,8 +3306,9 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val
>  u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
>  void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
>  u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
> -u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
> -void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
> +u32 vlv_gpio_read(struct drm_i915_private *dev_priv, u8 core_offset, u32 reg);
> +void vlv_gpio_write(struct drm_i915_private *dev_priv, u8 core_offset,
> +			u32 reg, u32 val);
>  u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
>  void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>  u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 313b1f9..3efea0e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -554,6 +554,11 @@
>  #define   IOSF_PORT_DPIO			0x12
>  #define   IOSF_PORT_DPIO_2			0x1a
>  #define   IOSF_PORT_GPIO_NC			0x13
> +#define   IOSF_PORT_GPIO_SC			0x48
> +#define   IOSF_PORT_GPIO_SUS			0xA8
> +#define   MAX_GPIO_NUM_NC			26
> +#define   MAX_GPIO_NUM_SC			128
> +#define   MAX_GPIO_NUM				172
>  #define   IOSF_PORT_CCK				0x14
>  #define   IOSF_PORT_CCU				0xA9
>  #define   IOSF_PORT_GPS_CORE			0x48
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index 2784ac4..13d3d22 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -34,6 +34,361 @@
>  #define DSI_DUAL_LINK_FRONT_BACK	1
>  #define DSI_DUAL_LINK_PIXEL_ALT		2
>  
> +#define HV_DDI0_HPD_GPIONC_0_PCONF0		0x4130
> +#define HV_DDI0_HPD_GPIONC_0_PAD		0x4138
> +#define HV_DDI0_DDC_SDA_GPIONC_1_PCONF0		0x4120
> +#define HV_DDI0_DDC_SDA_GPIONC_1_PAD		0x4128
> +#define HV_DDI0_DDC_SCL_GPIONC_2_PCONF0		0x4110
> +#define HV_DDI0_DDC_SCL_GPIONC_2_PAD		0x4118
> +#define PANEL0_VDDEN_GPIONC_3_PCONF0		0x4140
> +#define PANEL0_VDDEN_GPIONC_3_PAD		0x4148
> +#define PANEL0_BKLTEN_GPIONC_4_PCONF0		0x4150
> +#define PANEL0_BKLTEN_GPIONC_4_PAD		0x4158
> +#define PANEL0_BKLTCTL_GPIONC_5_PCONF0		0x4160
> +#define PANEL0_BKLTCTL_GPIONC_5_PAD		0x4168
> +#define HV_DDI1_HPD_GPIONC_6_PCONF0		0x4180
> +#define HV_DDI1_HPD_GPIONC_6_PAD		0x4188
> +#define HV_DDI1_DDC_SDA_GPIONC_7_PCONF0		0x4190
> +#define HV_DDI1_DDC_SDA_GPIONC_7_PAD		0x4198
> +#define HV_DDI1_DDC_SCL_GPIONC_8_PCONF0		0x4170
> +#define HV_DDI1_DDC_SCL_GPIONC_8_PAD		0x4178
> +#define PANEL1_VDDEN_GPIONC_9_PCONF0		0x4100
> +#define PANEL1_VDDEN_GPIONC_9_PAD		0x4108
> +#define PANEL1_BKLTEN_GPIONC_10_PCONF0		0x40E0
> +#define PANEL1_BKLTEN_GPIONC_10_PAD		0x40E8
> +#define PANEL1_BKLTCTL_GPIONC_11_PCONF0		0x40F0
> +#define PANEL1_BKLTCTL_GPIONC_11_PAD		0x40F8
> +#define GP_INTD_DSI_TE1_GPIONC_12_PCONF0	0x40C0
> +#define GP_INTD_DSI_TE1_GPIONC_12_PAD		0x40C8
> +#define HV_DDI2_DDC_SDA_GPIONC_13_PCONF0	0x41A0
> +#define HV_DDI2_DDC_SDA_GPIONC_13_PAD		0x41A8
> +#define HV_DDI2_DDC_SCL_GPIONC_14_PCONF0	0x41B0
> +#define HV_DDI2_DDC_SCL_GPIONC_14_PAD		0x41B8
> +#define GP_CAMERASB00_GPIONC_15_PCONF0		0x4010
> +#define GP_CAMERASB00_GPIONC_15_PAD		0x4018
> +#define GP_CAMERASB01_GPIONC_16_PCONF0		0x4040
> +#define GP_CAMERASB01_GPIONC_16_PAD		0x4048
> +#define GP_CAMERASB02_GPIONC_17_PCONF0		0x4080
> +#define GP_CAMERASB02_GPIONC_17_PAD		0x4088
> +#define GP_CAMERASB03_GPIONC_18_PCONF0		0x40B0
> +#define GP_CAMERASB03_GPIONC_18_PAD		0x40B8
> +#define GP_CAMERASB04_GPIONC_19_PCONF0		0x4000
> +#define GP_CAMERASB04_GPIONC_19_PAD		0x4008
> +#define GP_CAMERASB05_GPIONC_20_PCONF0		0x4030
> +#define GP_CAMERASB05_GPIONC_20_PAD		0x4038
> +#define GP_CAMERASB06_GPIONC_21_PCONF0		0x4060
> +#define GP_CAMERASB06_GPIONC_21_PAD		0x4068
> +#define GP_CAMERASB07_GPIONC_22_PCONF0		0x40A0
> +#define GP_CAMERASB07_GPIONC_22_PAD		0x40A8
> +#define GP_CAMERASB08_GPIONC_23_PCONF0		0x40D0
> +#define GP_CAMERASB08_GPIONC_23_PAD		0x40D8
> +#define GP_CAMERASB09_GPIONC_24_PCONF0		0x4020
> +#define GP_CAMERASB09_GPIONC_24_PAD		0x4028
> +#define GP_CAMERASB10_GPIONC_25_PCONF0		0x4050
> +#define GP_CAMERASB10_GPIONC_25_PAD		0x4058
> +#define GP_CAMERASB11_GPIONC_26_PCONF0		0x4090
> +#define GP_CAMERASB11_GPIONC_26_PAD		0x4098
> +
> +#define SATA_GP0_GPIOC_0_PCONF0			0x4550
> +#define SATA_GP0_GPIOC_0_PAD			0x4558
> +#define SATA_GP1_GPIOC_1_PCONF0			0x4590
> +#define SATA_GP1_GPIOC_1_PAD			0x4598
> +#define SATA_LEDN_GPIOC_2_PCONF0		0x45D0
> +#define SATA_LEDN_GPIOC_2_PAD			0x45D8
> +#define PCIE_CLKREQ0B_GPIOC_3_PCONF0		0x4600
> +#define PCIE_CLKREQ0B_GPIOC_3_PAD		0x4608
> +#define PCIE_CLKREQ1B_GPIOC_4_PCONF0		0x4630
> +#define PCIE_CLKREQ1B_GPIOC_4_PAD		0x4638
> +#define PCIE_CLKREQ2B_GPIOC_5_PCONF0		0x4660
> +#define PCIE_CLKREQ2B_GPIOC_5_PAD		0x4668
> +#define PCIE_CLKREQ3B_GPIOC_6_PCONF0		0x4620
> +#define PCIE_CLKREQ3B_GPIOC_6_PAD		0x4628
> +#define PCIE_CLKREQ4B_GPIOC_7_PCONF0		0x4650
> +#define PCIE_CLKREQ4B_GPIOC_7_PAD		0x4658
> +#define HDA_RSTB_GPIOC_8_PCONF0			0x4220
> +#define HDA_RSTB_GPIOC_8_PAD			0x4228
> +#define HDA_SYNC_GPIOC_9_PCONF0			0x4250
> +#define HDA_SYNC_GPIOC_9_PAD			0x4258
> +#define HDA_CLK_GPIOC_10_PCONF0			0x4240
> +#define HDA_CLK_GPIOC_10_PAD			0x4248
> +#define HDA_SDO_GPIOC_11_PCONF0			0x4260
> +#define HDA_SDO_GPIOC_11_PAD			0x4268
> +#define HDA_SDI0_GPIOC_12_PCONF0		0x4270
> +#define HDA_SDI0_GPIOC_12_PAD			0x4278
> +#define HDA_SDI1_GPIOC_13_PCONF0		0x4230
> +#define HDA_SDI1_GPIOC_13_PAD			0x4238
> +#define HDA_DOCKRSTB_GPIOC_14_PCONF0		0x4280
> +#define HDA_DOCKRSTB_GPIOC_14_PAD		0x4288
> +#define HDA_DOCKENB_GPIOC_15_PCONF0		0x4540
> +#define HDA_DOCKENB_GPIOC_15_PAD		0x4548
> +#define SDMMC1_CLK_GPIOC_16_PCONF0		0x43E0
> +#define SDMMC1_CLK_GPIOC_16_PAD			0x43E8
> +#define SDMMC1_D0_GPIOC_17_PCONF0		0x43D0
> +#define SDMMC1_D0_GPIOC_17_PAD			0x43D8
> +#define SDMMC1_D1_GPIOC_18_PCONF0		0x4400
> +#define SDMMC1_D1_GPIOC_18_PAD			0x4408
> +#define SDMMC1_D2_GPIOC_19_PCONF0		0x43B0
> +#define SDMMC1_D2_GPIOC_19_PAD			0x43B8
> +#define SDMMC1_D3_CD_B_GPIOC_20_PCONF0		0x4360
> +#define SDMMC1_D3_CD_B_GPIOC_20_PAD		0x4368
> +#define MMC1_D4_SD_WE_GPIOC_21_PCONF0		0x4380
> +#define MMC1_D4_SD_WE_GPIOC_21_PAD		0x4388
> +#define MMC1_D5_GPIOC_22_PCONF0			0x43C0
> +#define MMC1_D5_GPIOC_22_PAD			0x43C8
> +#define MMC1_D6_GPIOC_23_PCONF0			0x4370
> +#define MMC1_D6_GPIOC_23_PAD			0x4378
> +#define MMC1_D7_GPIOC_24_PCONF0			0x43F0
> +#define MMC1_D7_GPIOC_24_PAD			0x43F8
> +#define SDMMC1_CMD_GPIOC_25_PCONF0		0x4390
> +#define SDMMC1_CMD_GPIOC_25_PAD			0x4398
> +#define MMC1_RESET_B_GPIOC_26_PCONF0		0x4330
> +#define MMC1_RESET_B_GPIOC_26_PAD		0x4338
> +#define SDMMC2_CLK_GPIOC_27_PCONF0		0x4320
> +#define SDMMC2_CLK_GPIOC_27_PAD			0x4328
> +#define SDMMC2_D0_GPIOC_28_PCONF0		0x4350
> +#define SDMMC2_D0_GPIOC_28_PAD			0x4358
> +#define SDMMC2_D1_GPIOC_29_PCONF0		0x42F0
> +#define SDMMC2_D1_GPIOC_29_PAD			0x42F8
> +#define SDMMC2_D2_GPIOC_30_PCONF0		0x4340
> +#define SDMMC2_D2_GPIOC_30_PAD			0x4348
> +#define SDMMC2_D3_CD_B_GPIOC_31_PCONF0		0x4310
> +#define SDMMC2_D3_CD_B_GPIOC_31_PAD		0x4318
> +#define SDMMC2_CMD_GPIOC_32_PCONF0		0x4300
> +#define SDMMC2_CMD_GPIOC_32_PAD			0x4308
> +#define SDMMC3_CLK_GPIOC_33_PCONF0		0x42B0
> +#define SDMMC3_CLK_GPIOC_33_PAD			0x42B8
> +#define SDMMC3_D0_GPIOC_34_PCONF0		0x42E0
> +#define SDMMC3_D0_GPIOC_34_PAD			0x42E8
> +#define SDMMC3_D1_GPIOC_35_PCONF0		0x4290
> +#define SDMMC3_D1_GPIOC_35_PAD			0x4298
> +#define SDMMC3_D2_GPIOC_36_PCONF0		0x42D0
> +#define SDMMC3_D2_GPIOC_36_PAD			0x42D8
> +#define SDMMC3_D3_GPIOC_37_PCONF0		0x42A0
> +#define SDMMC3_D3_GPIOC_37_PAD			0x42A8
> +#define SDMMC3_CD_B_GPIOC_38_PCONF0		0x43A0
> +#define SDMMC3_CD_B_GPIOC_38_PAD		0x43A8
> +#define SDMMC3_CMD_GPIOC_39_PCONF0		0x42C0
> +#define SDMMC3_CMD_GPIOC_39_PAD			0x42C8
> +#define SDMMC3_1P8_EN_GPIOC_40_PCONF0		0x45F0
> +#define SDMMC3_1P8_EN_GPIOC_40_PAD		0x45F8
> +#define SDMMC3_PWR_EN_B_GPIOC_41_PCONF0		0x4690
> +#define SDMMC3_PWR_EN_B_GPIOC_41_PAD		0x4698
> +#define LPC_AD0_GPIOC_42_PCONF0			0x4460
> +#define LPC_AD0_GPIOC_42_PAD			0x4468
> +#define LPC_AD1_GPIOC_43_PCONF0			0x4440
> +#define LPC_AD1_GPIOC_43_PAD			0x4448
> +#define LPC_AD2_GPIOC_44_PCONF0			0x4430
> +#define LPC_AD2_GPIOC_44_PAD			0x4438
> +#define LPC_AD3_GPIOC_45_PCONF0			0x4420
> +#define LPC_AD3_GPIOC_45_PAD			0x4428
> +#define LPC_FRAMEB_GPIOC_46_PCONF0		0x4450
> +#define LPC_FRAMEB_GPIOC_46_PAD			0x4458
> +#define LPC_CLKOUT0_GPIOC_47_PCONF0		0x4470
> +#define LPC_CLKOUT0_GPIOC_47_PAD		0x4478
> +#define LPC_CLKOUT1_GPIOC_48_PCONF0		0x4410
> +#define LPC_CLKOUT1_GPIOC_48_PAD		0x4418
> +#define LPC_CLKRUNB_GPIOC_49_PCONF0		0x4480
> +#define LPC_CLKRUNB_GPIOC_49_PAD		0x4488
> +#define ILB_SERIRQ_GPIOC_50_PCONF0		0x4560
> +#define ILB_SERIRQ_GPIOC_50_PAD			0x4568
> +#define SMB_DATA_GPIOC_51_PCONF0		0x45A0
> +#define SMB_DATA_GPIOC_51_PAD			0x45A8
> +#define SMB_CLK_GPIOC_52_PCONF0			0x4580
> +#define SMB_CLK_GPIOC_52_PAD			0x4588
> +#define SMB_ALERTB_GPIOC_53_PCONF0		0x45C0
> +#define SMB_ALERTB_GPIOC_53_PAD			0x45C8
> +#define SPKR_GPIOC_54_PCONF0			0x4670
> +#define SPKR_GPIOC_54_PAD			0x4678
> +#define MHSI_ACDATA_GPIOC_55_PCONF0		0x44D0
> +#define MHSI_ACDATA_GPIOC_55_PAD		0x44D8
> +#define MHSI_ACFLAG_GPIOC_56_PCONF0		0x44F0
> +#define MHSI_ACFLAG_GPIOC_56_PAD		0x44F8
> +#define MHSI_ACREADY_GPIOC_57_PCONF0		0x4530
> +#define MHSI_ACREADY_GPIOC_57_PAD		0x4538
> +#define MHSI_ACWAKE_GPIOC_58_PCONF0		0x44E0
> +#define MHSI_ACWAKE_GPIOC_58_PAD		0x44E8
> +#define MHSI_CADATA_GPIOC_59_PCONF0		0x4510
> +#define MHSI_CADATA_GPIOC_59_PAD		0x4518
> +#define MHSI_CAFLAG_GPIOC_60_PCONF0		0x4500
> +#define MHSI_CAFLAG_GPIOC_60_PAD		0x4508
> +#define MHSI_CAREADY_GPIOC_61_PCONF0		0x4520
> +#define MHSI_CAREADY_GPIOC_61_PAD		0x4528
> +#define GP_SSP_2_CLK_GPIOC_62_PCONF0		0x40D0
> +#define GP_SSP_2_CLK_GPIOC_62_PAD		0x40D8
> +#define GP_SSP_2_FS_GPIOC_63_PCONF0		0x40C0
> +#define GP_SSP_2_FS_GPIOC_63_PAD		0x40C8
> +#define GP_SSP_2_RXD_GPIOC_64_PCONF0		0x40F0
> +#define GP_SSP_2_RXD_GPIOC_64_PAD		0x40F8
> +#define GP_SSP_2_TXD_GPIOC_65_PCONF0		0x40E0
> +#define GP_SSP_2_TXD_GPIOC_65_PAD		0x40E8
> +#define SPI1_CS0_B_GPIOC_66_PCONF0		0x4110
> +#define SPI1_CS0_B_GPIOC_66_PAD			0x4118
> +#define SPI1_MISO_GPIOC_67_PCONF0		0x4120
> +#define SPI1_MISO_GPIOC_67_PAD			0x4128
> +#define SPI1_MOSI_GPIOC_68_PCONF0		0x4130
> +#define SPI1_MOSI_GPIOC_68_PAD			0x4138
> +#define SPI1_CLK_GPIOC_69_PCONF0		0x4100
> +#define SPI1_CLK_GPIOC_69_PAD			0x4108
> +#define UART1_RXD_GPIOC_70_PCONF0		0x4020
> +#define UART1_RXD_GPIOC_70_PAD			0x4028
> +#define UART1_TXD_GPIOC_71_PCONF0		0x4010
> +#define UART1_TXD_GPIOC_71_PAD			0x4018
> +#define UART1_RTS_B_GPIOC_72_PCONF0		0x4000
> +#define UART1_RTS_B_GPIOC_72_PAD		0x4008
> +#define UART1_CTS_B_GPIOC_73_PCONF0		0x4040
> +#define UART1_CTS_B_GPIOC_73_PAD		0x4048
> +#define UART2_RXD_GPIOC_74_PCONF0		0x4060
> +#define UART2_RXD_GPIOC_74_PAD			0x4068
> +#define UART2_TXD_GPIOC_75_PCONF0		0x4070
> +#define UART2_TXD_GPIOC_75_PAD			0x4078
> +#define UART2_RTS_B_GPIOC_76_PCONF0		0x4090
> +#define UART2_RTS_B_GPIOC_76_PAD		0x4098
> +#define UART2_CTS_B_GPIOC_77_PCONF0		0x4080
> +#define UART2_CTS_B_GPIOC_77_PAD		0x4088
> +#define I2C0_SDA_GPIOC_78_PCONF0		0x4210
> +#define I2C0_SDA_GPIOC_78_PAD			0x4218
> +#define I2C0_SCL_GPIOC_79_PCONF0		0x4200
> +#define I2C0_SCL_GPIOC_79_PAD			0x4208
> +#define I2C1_SDA_GPIOC_80_PCONF0		0x41F0
> +#define I2C1_SDA_GPIOC_80_PAD			0x41F8
> +#define I2C1_SCL_GPIOC_81_PCONF0		0x41E0
> +#define I2C1_SCL_GPIOC_81_PAD			0x41E8
> +#define I2C2_SDA_GPIOC_82_PCONF0		0x41D0
> +#define I2C2_SDA_GPIOC_82_PAD			0x41D8
> +#define I2C2_SCL_GPIOC_83_PCONF0		0x41B0
> +#define I2C2_SCL_GPIOC_83_PAD			0x41B8
> +#define I2C3_SDA_GPIOC_84_PCONF0		0x4190
> +#define I2C2_SCL_GPIOC_83_PAD			0x41B8
> +#define I2C3_SDA_GPIOC_84_PCONF0		0x4190
> +#define I2C3_SDA_GPIOC_84_PAD			0x4198
> +#define I2C3_SCL_GPIOC_85_PCONF0		0x41C0
> +#define I2C3_SCL_GPIOC_85_PAD			0x41C8
> +#define I2C4_SDA_GPIOC_86_PCONF0		0x41A0
> +#define I2C4_SDA_GPIOC_86_PAD			0x41A8
> +#define I2C4_SCL_GPIOC_87_PCONF0		0x4170
> +#define I2C4_SCL_GPIOC_87_PAD			0x4178
> +#define I2C5_SDA_GPIOC_88_PCONF0		0x4150
> +#define I2C5_SDA_GPIOC_88_PAD			0x4158
> +#define I2C5_SCL_GPIOC_89_PCONF0		0x4140
> +#define I2C5_SCL_GPIOC_89_PAD			0x4148
> +#define I2C6_SDA_GPIOC_90_PCONF0		0x4180
> +#define I2C6_SDA_GPIOC_90_PAD			0x4188
> +#define I2C6_SCL_GPIOC_91_PCONF0		0x4160
> +#define I2C6_SCL_GPIOC_91_PAD			0x4168
> +#define I2C_NFC_SDA_GPIOC_92_PCONF0		0x4050
> +#define I2C_NFC_SDA_GPIOC_92_PAD		0x4058
> +#define I2C_NFC_SCL_GPIOC_93_PCONF0		0x4030
> +#define I2C_NFC_SCL_GPIOC_93_PAD		0x4038
> +#define PWM0_GPIOC_94_PCONF0			0x40A0
> +#define PWM0_GPIOC_94_PAD			0x40A8
> +#define PWM1_GPIOC_95_PCONF0			0x40B0
> +#define PWM1_GPIOC_95_PAD			0x40B8
> +#define PLT_CLK0_GPIOC_96_PCONF0		0x46A0
> +#define PLT_CLK0_GPIOC_96_PAD			0x46A8
> +#define PLT_CLK1_GPIOC_97_PCONF0		0x4570
> +#define PLT_CLK1_GPIOC_97_PAD			0x4578
> +#define PLT_CLK2_GPIOC_98_PCONF0		0x45B0
> +#define PLT_CLK2_GPIOC_98_PAD			0x45B8
> +#define PLT_CLK3_GPIOC_99_PCONF0		0x4680
> +#define PLT_CLK3_GPIOC_99_PAD			0x4688
> +#define PLT_CLK4_GPIOC_100_PCONF0		0x4610
> +#define PLT_CLK4_GPIOC_100_PAD			0x4618
> +#define PLT_CLK5_GPIOC_101_PCONF0		0x4640
> +#define PLT_CLK5_GPIOC_101_PAD			0x4648
> +
> +#define GPIO_SUS0_GPIO_SUS0_PCONF0		0x41D0
> +#define GPIO_SUS0_GPIO_SUS0_PAD			0x41D8
> +#define GPIO_SUS1_GPIO_SUS1_PCONF0		0x4210
> +#define GPIO_SUS1_GPIO_SUS1_PAD			0x4218
> +#define GPIO_SUS2_GPIO_SUS2_PCONF0		0x41E0
> +#define GPIO_SUS2_GPIO_SUS2_PAD			0x41E8
> +#define GPIO_SUS3_GPIO_SUS3_PCONF0		0x41F0
> +#define GPIO_SUS3_GPIO_SUS3_PAD			0x41F8
> +#define GPIO_SUS4_GPIO_SUS4_PCONF0		0x4200
> +#define GPIO_SUS4_GPIO_SUS4_PAD			0x4208
> +#define GPIO_SUS5_GPIO_SUS5_PCONF0		0x4220
> +#define GPIO_SUS5_GPIO_SUS5_PAD			0x4228
> +#define GPIO_SUS6_GPIO_SUS6_PCONF0		0x4240
> +#define GPIO_SUS6_GPIO_SUS6_PAD			0x4248
> +#define GPIO_SUS7_GPIO_SUS7_PCONF0		0x4230
> +#define GPIO_SUS7_GPIO_SUS7_PAD			0x4238
> +#define SEC_GPIO_SUS8_GPIO_SUS8_PCONF0		0x4260
> +#define SEC_GPIO_SUS8_GPIO_SUS8_PAD		0x4268
> +#define SEC_GPIO_SUS9_GPIO_SUS9_PCONF0		0x4250
> +#define SEC_GPIO_SUS9_GPIO_SUS9_PAD		0x4258
> +#define SEC_GPIO_SUS10_GPIO_SUS10_PCONF0	0x4120
> +#define SEC_GPIO_SUS10_GPIO_SUS10_PAD		0x4128
> +#define SUSPWRDNACK_GPIOS_11_PCONF0		0x4070
> +#define SUSPWRDNACK_GPIOS_11_PAD		0x4078
> +#define PMU_SUSCLK_GPIOS_12_PCONF0		0x40B0
> +#define PMU_SUSCLK_GPIOS_12_PAD			0x40B8
> +#define PMU_SLP_S0IX_B_GPIOS_13_PCONF0		0x4140
> +#define PMU_SLP_S0IX_B_GPIOS_13_PAD		0x4148
> +#define PMU_SLP_LAN_B_GPIOS_14_PCONF0		0x4110
> +#define PMU_SLP_LAN_B_GPIOS_14_PAD		0x4118
> +#define PMU_WAKE_B_GPIOS_15_PCONF0		0x4010
> +#define PMU_WAKE_B_GPIOS_15_PAD			0x4018
> +#define PMU_PWRBTN_B_GPIOS_16_PCONF0		0x4080
> +#define PMU_PWRBTN_B_GPIOS_16_PAD		0x4088
> +#define PMU_WAKE_LAN_B_GPIOS_17_PCONF0		0x40A0
> +#define PMU_WAKE_LAN_B_GPIOS_17_PAD		0x40A8
> +#define SUS_STAT_B_GPIOS_18_PCONF0		0x4130
> +#define SUS_STAT_B_GPIOS_18_PAD			0x4138
> +#define USB_OC0_B_GPIOS_19_PCONF0		0x40C0
> +#define USB_OC0_B_GPIOS_19_PAD			0x40C8
> +#define USB_OC1_B_GPIOS_20_PCONF0		0x4000
> +#define USB_OC1_B_GPIOS_20_PAD			0x4008
> +#define SPI_CS1_B_GPIOS_21_PCONF0		0x4020
> +#define SPI_CS1_B_GPIOS_21_PAD			0x4028
> +#define GPIO_DFX0_GPIOS_22_PCONF0		0x4170
> +#define GPIO_DFX0_GPIOS_22_PAD			0x4178
> +#define GPIO_DFX1_GPIOS_23_PCONF0		0x4270
> +#define GPIO_DFX1_GPIOS_23_PAD			0x4278
> +#define GPIO_DFX2_GPIOS_24_PCONF0		0x41C0
> +#define GPIO_DFX2_GPIOS_24_PAD			0x41C8
> +#define GPIO_DFX3_GPIOS_25_PCONF0		0x41B0
> +#define GPIO_DFX3_GPIOS_25_PAD			0x41B8
> +#define GPIO_DFX4_GPIOS_26_PCONF0		0x4160
> +#define GPIO_DFX4_GPIOS_26_PAD			0x4168
> +#define GPIO_DFX5_GPIOS_27_PCONF0		0x4150
> +#define GPIO_DFX5_GPIOS_27_PAD			0x4158
> +#define GPIO_DFX6_GPIOS_28_PCONF0		0x4180
> +#define GPIO_DFX6_GPIOS_28_PAD			0x4188
> +#define GPIO_DFX7_GPIOS_29_PCONF0		0x4190
> +#define GPIO_DFX7_GPIOS_29_PAD			0x4198
> +#define GPIO_DFX8_GPIOS_30_PCONF0		0x41A0
> +#define GPIO_DFX8_GPIOS_30_PAD			0x41A8
> +#define USB_ULPI_0_CLK_GPIOS_31_PCONF0		0x4330
> +#define USB_ULPI_0_CLK_GPIOS_31_PAD		0x4338
> +#define USB_ULPI_0_DATA0_GPIOS_32_PCONF0	0x4380
> +#define USB_ULPI_0_DATA0_GPIOS_32_PAD		0x4388
> +#define USB_ULPI_0_DATA1_GPIOS_33_PCONF0	0x4360
> +#define USB_ULPI_0_DATA1_GPIOS_33_PAD		0x4368
> +#define USB_ULPI_0_DATA2_GPIOS_34_PCONF0	0x4310
> +#define USB_ULPI_0_DATA2_GPIOS_34_PAD		0x4318
> +#define USB_ULPI_0_DATA3_GPIOS_35_PCONF0	0x4370
> +#define USB_ULPI_0_DATA3_GPIOS_35_PAD		0x4378
> +#define USB_ULPI_0_DATA4_GPIOS_36_PCONF0	0x4300
> +#define USB_ULPI_0_DATA4_GPIOS_36_PAD		0x4308
> +#define USB_ULPI_0_DATA5_GPIOS_37_PCONF0	0x4390
> +#define USB_ULPI_0_DATA5_GPIOS_37_PAD		0x4398
> +#define USB_ULPI_0_DATA6_GPIOS_38_PCONF0	0x4320
> +#define USB_ULPI_0_DATA6_GPIOS_38_PAD		0x4328
> +#define USB_ULPI_0_DATA7_GPIOS_39_PCONF0	0x43A0
> +#define USB_ULPI_0_DATA7_GPIOS_39_PAD		0x43A8
> +#define USB_ULPI_0_DIR_GPIOS_40_PCONF0		0x4340
> +#define USB_ULPI_0_DIR_GPIOS_40_PAD		0x4348
> +#define USB_ULPI_0_NXT_GPIOS_41_PCONF0		0x4350
> +#define USB_ULPI_0_NXT_GPIOS_41_PAD		0x4358
> +#define USB_ULPI_0_STP_GPIOS_42_PCONF0		0x43B0
> +#define USB_ULPI_0_STP_GPIOS_42_PAD		0x43B8
> +#define USB_ULPI_0_REFCLK_GPIOS_43_PCONF0	0x4280
> +#define USB_ULPI_0_REFCLK_GPIOS_43_PAD		0x4288
> +
> +#define PMIC_PANEL_EN		0x52
> +#define PMIC_PWM_EN		0x51
> +#define PMIC_BKL_EN		0x4B
> +#define PMIC_PWM_LEVEL		0x4E
>  struct intel_dsi_host;
>  
>  struct intel_dsi {
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index 7e0ba74..f2ea875 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -91,18 +91,181 @@ struct gpio_table {
>  };
>  
>  static struct gpio_table gtable[] = {
> -	{ GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
> -	{ GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
> -	{ GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
> -	{ GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 },
> -	{ GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 },
> -	{ GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 },
> -	{ GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
> -	{ GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
> -	{ GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
> -	{ GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
> -	{ GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
> -	{ GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
> +	{HV_DDI0_HPD_GPIONC_0_PCONF0, HV_DDI0_HPD_GPIONC_0_PAD, 0},
> +	{HV_DDI0_DDC_SDA_GPIONC_1_PCONF0, HV_DDI0_DDC_SDA_GPIONC_1_PAD, 0},
> +	{HV_DDI0_DDC_SCL_GPIONC_2_PCONF0, HV_DDI0_DDC_SCL_GPIONC_2_PAD, 0},
> +	{PANEL0_VDDEN_GPIONC_3_PCONF0, PANEL0_VDDEN_GPIONC_3_PAD, 0},
> +	{PANEL0_BKLTEN_GPIONC_4_PCONF0, PANEL0_BKLTEN_GPIONC_4_PAD, 0},
> +	{PANEL0_BKLTCTL_GPIONC_5_PCONF0, PANEL0_BKLTCTL_GPIONC_5_PAD, 0},
> +	{HV_DDI1_HPD_GPIONC_6_PCONF0, HV_DDI1_HPD_GPIONC_6_PAD, 0},
> +	{HV_DDI1_DDC_SDA_GPIONC_7_PCONF0, HV_DDI1_DDC_SDA_GPIONC_7_PAD, 0},
> +	{HV_DDI1_DDC_SCL_GPIONC_8_PCONF0, HV_DDI1_DDC_SCL_GPIONC_8_PAD, 0},
> +	{PANEL1_VDDEN_GPIONC_9_PCONF0, PANEL1_VDDEN_GPIONC_9_PAD, 0},
> +	{PANEL1_BKLTEN_GPIONC_10_PCONF0, PANEL1_BKLTEN_GPIONC_10_PAD, 0},
> +	{PANEL1_BKLTCTL_GPIONC_11_PCONF0, PANEL1_BKLTCTL_GPIONC_11_PAD, 0},
> +	{GP_INTD_DSI_TE1_GPIONC_12_PCONF0, GP_INTD_DSI_TE1_GPIONC_12_PAD, 0},
> +	{HV_DDI2_DDC_SDA_GPIONC_13_PCONF0, HV_DDI2_DDC_SDA_GPIONC_13_PAD, 0},
> +	{HV_DDI2_DDC_SCL_GPIONC_14_PCONF0, HV_DDI2_DDC_SCL_GPIONC_14_PAD, 0},
> +	{GP_CAMERASB00_GPIONC_15_PCONF0, GP_CAMERASB00_GPIONC_15_PAD, 0},
> +	{GP_CAMERASB01_GPIONC_16_PCONF0, GP_CAMERASB01_GPIONC_16_PAD, 0},
> +	{GP_CAMERASB02_GPIONC_17_PCONF0, GP_CAMERASB02_GPIONC_17_PAD, 0},
> +	{GP_CAMERASB03_GPIONC_18_PCONF0, GP_CAMERASB03_GPIONC_18_PAD, 0},
> +	{GP_CAMERASB04_GPIONC_19_PCONF0, GP_CAMERASB04_GPIONC_19_PAD, 0},
> +	{GP_CAMERASB05_GPIONC_20_PCONF0, GP_CAMERASB05_GPIONC_20_PAD, 0},
> +	{GP_CAMERASB06_GPIONC_21_PCONF0, GP_CAMERASB06_GPIONC_21_PAD, 0},
> +	{GP_CAMERASB07_GPIONC_22_PCONF0, GP_CAMERASB07_GPIONC_22_PAD, 0},
> +	{GP_CAMERASB08_GPIONC_23_PCONF0, GP_CAMERASB08_GPIONC_23_PAD, 0},
> +	{GP_CAMERASB09_GPIONC_24_PCONF0, GP_CAMERASB09_GPIONC_24_PAD, 0},
> +	{GP_CAMERASB10_GPIONC_25_PCONF0, GP_CAMERASB10_GPIONC_25_PAD, 0},
> +	{GP_CAMERASB11_GPIONC_26_PCONF0, GP_CAMERASB11_GPIONC_26_PAD, 0},
> +
> +	{SATA_GP0_GPIOC_0_PCONF0, SATA_GP0_GPIOC_0_PAD, 0},
> +	{SATA_GP1_GPIOC_1_PCONF0, SATA_GP1_GPIOC_1_PAD, 0},
> +	{SATA_LEDN_GPIOC_2_PCONF0, SATA_LEDN_GPIOC_2_PAD, 0},
> +	{PCIE_CLKREQ0B_GPIOC_3_PCONF0, PCIE_CLKREQ0B_GPIOC_3_PAD, 0},
> +	{PCIE_CLKREQ1B_GPIOC_4_PCONF0, PCIE_CLKREQ1B_GPIOC_4_PAD, 0},
> +	{PCIE_CLKREQ2B_GPIOC_5_PCONF0, PCIE_CLKREQ2B_GPIOC_5_PAD, 0},
> +	{PCIE_CLKREQ3B_GPIOC_6_PCONF0, PCIE_CLKREQ3B_GPIOC_6_PAD, 0},
> +	{PCIE_CLKREQ4B_GPIOC_7_PCONF0, PCIE_CLKREQ4B_GPIOC_7_PAD, 0},
> +	{HDA_RSTB_GPIOC_8_PCONF0, HDA_RSTB_GPIOC_8_PAD, 0},
> +	{HDA_SYNC_GPIOC_9_PCONF0, HDA_SYNC_GPIOC_9_PAD, 0},
> +	{HDA_CLK_GPIOC_10_PCONF0, HDA_CLK_GPIOC_10_PAD, 0},
> +	{HDA_SDO_GPIOC_11_PCONF0, HDA_SDO_GPIOC_11_PAD, 0},
> +	{HDA_SDI0_GPIOC_12_PCONF0, HDA_SDI0_GPIOC_12_PAD, 0},
> +	{HDA_SDI1_GPIOC_13_PCONF0, HDA_SDI1_GPIOC_13_PAD, 0},
> +	{HDA_DOCKRSTB_GPIOC_14_PCONF0, HDA_DOCKRSTB_GPIOC_14_PAD, 0},
> +	{HDA_DOCKENB_GPIOC_15_PCONF0, HDA_DOCKENB_GPIOC_15_PAD, 0},
> +	{SDMMC1_CLK_GPIOC_16_PCONF0, SDMMC1_CLK_GPIOC_16_PAD, 0},
> +	{SDMMC1_D0_GPIOC_17_PCONF0, SDMMC1_D0_GPIOC_17_PAD, 0},
> +	{SDMMC1_D1_GPIOC_18_PCONF0, SDMMC1_D1_GPIOC_18_PAD, 0},
> +	{SDMMC1_D2_GPIOC_19_PCONF0, SDMMC1_D2_GPIOC_19_PAD, 0},
> +	{SDMMC1_D3_CD_B_GPIOC_20_PCONF0, SDMMC1_D3_CD_B_GPIOC_20_PAD, 0},
> +	{MMC1_D4_SD_WE_GPIOC_21_PCONF0, MMC1_D4_SD_WE_GPIOC_21_PAD, 0},
> +	{MMC1_D5_GPIOC_22_PCONF0, MMC1_D5_GPIOC_22_PAD, 0},
> +	{MMC1_D6_GPIOC_23_PCONF0, MMC1_D6_GPIOC_23_PAD, 0},
> +	{MMC1_D7_GPIOC_24_PCONF0, MMC1_D7_GPIOC_24_PAD, 0},
> +	{SDMMC1_CMD_GPIOC_25_PCONF0, SDMMC1_CMD_GPIOC_25_PAD, 0},
> +	{MMC1_RESET_B_GPIOC_26_PCONF0, MMC1_RESET_B_GPIOC_26_PAD, 0},
> +	{SDMMC2_CLK_GPIOC_27_PCONF0, SDMMC2_CLK_GPIOC_27_PAD, 0},
> +	{SDMMC2_D0_GPIOC_28_PCONF0, SDMMC2_D0_GPIOC_28_PAD, 0},
> +	{SDMMC2_D1_GPIOC_29_PCONF0, SDMMC2_D1_GPIOC_29_PAD, 0},
> +	{SDMMC2_D2_GPIOC_30_PCONF0, SDMMC2_D2_GPIOC_30_PAD, 0},
> +	{SDMMC2_D3_CD_B_GPIOC_31_PCONF0, SDMMC2_D3_CD_B_GPIOC_31_PAD, 0},
> +	{SDMMC2_CMD_GPIOC_32_PCONF0, SDMMC2_CMD_GPIOC_32_PAD, 0},
> +	{SDMMC3_CLK_GPIOC_33_PCONF0, SDMMC3_CLK_GPIOC_33_PAD, 0},
> +	{SDMMC3_D0_GPIOC_34_PCONF0, SDMMC3_D0_GPIOC_34_PAD, 0},
> +	{SDMMC3_D1_GPIOC_35_PCONF0, SDMMC3_D1_GPIOC_35_PAD, 0},
> +	{SDMMC3_D2_GPIOC_36_PCONF0, SDMMC3_D2_GPIOC_36_PAD, 0},
> +	{SDMMC3_D3_GPIOC_37_PCONF0, SDMMC3_D3_GPIOC_37_PAD, 0},
> +	{SDMMC3_CD_B_GPIOC_38_PCONF0, SDMMC3_CD_B_GPIOC_38_PAD, 0},
> +	{SDMMC3_CMD_GPIOC_39_PCONF0, SDMMC3_CMD_GPIOC_39_PAD, 0},
> +	{SDMMC3_1P8_EN_GPIOC_40_PCONF0, SDMMC3_1P8_EN_GPIOC_40_PAD, 0},
> +	{SDMMC3_PWR_EN_B_GPIOC_41_PCONF0, SDMMC3_PWR_EN_B_GPIOC_41_PAD, 0},
> +	{LPC_AD0_GPIOC_42_PCONF0, LPC_AD0_GPIOC_42_PAD, 0},
> +	{LPC_AD1_GPIOC_43_PCONF0, LPC_AD1_GPIOC_43_PAD, 0},
> +	{LPC_AD2_GPIOC_44_PCONF0, LPC_AD2_GPIOC_44_PAD, 0},
> +	{LPC_AD3_GPIOC_45_PCONF0, LPC_AD3_GPIOC_45_PAD, 0},
> +	{LPC_FRAMEB_GPIOC_46_PCONF0, LPC_FRAMEB_GPIOC_46_PAD, 0},
> +	{LPC_CLKOUT0_GPIOC_47_PCONF0, LPC_CLKOUT0_GPIOC_47_PAD, 0},
> +	{LPC_CLKOUT1_GPIOC_48_PCONF0, LPC_CLKOUT1_GPIOC_48_PAD, 0},
> +	{LPC_CLKRUNB_GPIOC_49_PCONF0, LPC_CLKRUNB_GPIOC_49_PAD, 0},
> +	{ILB_SERIRQ_GPIOC_50_PCONF0, ILB_SERIRQ_GPIOC_50_PAD, 0},
> +	{SMB_DATA_GPIOC_51_PCONF0, SMB_DATA_GPIOC_51_PAD, 0},
> +	{SMB_CLK_GPIOC_52_PCONF0, SMB_CLK_GPIOC_52_PAD, 0},
> +	{SMB_ALERTB_GPIOC_53_PCONF0, SMB_ALERTB_GPIOC_53_PAD, 0},
> +	{SPKR_GPIOC_54_PCONF0, SPKR_GPIOC_54_PAD, 0},
> +	{MHSI_ACDATA_GPIOC_55_PCONF0, MHSI_ACDATA_GPIOC_55_PAD, 0},
> +	{MHSI_ACFLAG_GPIOC_56_PCONF0, MHSI_ACFLAG_GPIOC_56_PAD, 0},
> +	{MHSI_ACREADY_GPIOC_57_PCONF0, MHSI_ACREADY_GPIOC_57_PAD, 0},
> +	{MHSI_ACWAKE_GPIOC_58_PCONF0, MHSI_ACWAKE_GPIOC_58_PAD, 0},
> +	{MHSI_CADATA_GPIOC_59_PCONF0, MHSI_CADATA_GPIOC_59_PAD, 0},
> +	{MHSI_CAFLAG_GPIOC_60_PCONF0, MHSI_CAFLAG_GPIOC_60_PAD, 0},
> +	{MHSI_CAREADY_GPIOC_61_PCONF0, MHSI_CAREADY_GPIOC_61_PAD, 0},
> +	{GP_SSP_2_CLK_GPIOC_62_PCONF0, GP_SSP_2_CLK_GPIOC_62_PAD, 0},
> +	{GP_SSP_2_FS_GPIOC_63_PCONF0, GP_SSP_2_FS_GPIOC_63_PAD, 0},
> +	{GP_SSP_2_RXD_GPIOC_64_PCONF0, GP_SSP_2_RXD_GPIOC_64_PAD, 0},
> +	{GP_SSP_2_TXD_GPIOC_65_PCONF0, GP_SSP_2_TXD_GPIOC_65_PAD, 0},
> +	{SPI1_CS0_B_GPIOC_66_PCONF0, SPI1_CS0_B_GPIOC_66_PAD, 0},
> +	{SPI1_MISO_GPIOC_67_PCONF0, SPI1_MISO_GPIOC_67_PAD, 0},
> +	{SPI1_MOSI_GPIOC_68_PCONF0, SPI1_MOSI_GPIOC_68_PAD, 0},
> +	{SPI1_CLK_GPIOC_69_PCONF0, SPI1_CLK_GPIOC_69_PAD, 0},
> +	{UART1_RXD_GPIOC_70_PCONF0, UART1_RXD_GPIOC_70_PAD, 0},
> +	{UART1_TXD_GPIOC_71_PCONF0, UART1_TXD_GPIOC_71_PAD, 0},
> +	{UART1_RTS_B_GPIOC_72_PCONF0, UART1_RTS_B_GPIOC_72_PAD, 0},
> +	{UART1_CTS_B_GPIOC_73_PCONF0, UART1_CTS_B_GPIOC_73_PAD, 0},
> +	{UART2_RXD_GPIOC_74_PCONF0, UART2_RXD_GPIOC_74_PAD, 0},
> +	{UART2_TXD_GPIOC_75_PCONF0, UART2_TXD_GPIOC_75_PAD, 0},
> +	{UART2_RTS_B_GPIOC_76_PCONF0, UART2_RTS_B_GPIOC_76_PAD, 0},
> +	{UART2_CTS_B_GPIOC_77_PCONF0, UART2_CTS_B_GPIOC_77_PAD, 0},
> +	{I2C0_SDA_GPIOC_78_PCONF0, I2C0_SDA_GPIOC_78_PAD, 0},
> +	{I2C0_SCL_GPIOC_79_PCONF0, I2C0_SCL_GPIOC_79_PAD, 0},
> +	{I2C1_SDA_GPIOC_80_PCONF0, I2C1_SDA_GPIOC_80_PAD, 0},
> +	{I2C1_SCL_GPIOC_81_PCONF0, I2C1_SCL_GPIOC_81_PAD, 0},
> +	{I2C2_SDA_GPIOC_82_PCONF0, I2C2_SDA_GPIOC_82_PAD, 0},
> +	{I2C2_SCL_GPIOC_83_PCONF0, I2C2_SCL_GPIOC_83_PAD, 0},
> +	{I2C3_SDA_GPIOC_84_PCONF0, I2C3_SDA_GPIOC_84_PAD, 0},
> +	{I2C3_SCL_GPIOC_85_PCONF0, I2C3_SCL_GPIOC_85_PAD, 0},
> +	{I2C4_SDA_GPIOC_86_PCONF0, I2C4_SDA_GPIOC_86_PAD, 0},
> +	{I2C4_SCL_GPIOC_87_PCONF0, I2C4_SCL_GPIOC_87_PAD, 0},
> +	{I2C5_SDA_GPIOC_88_PCONF0, I2C5_SDA_GPIOC_88_PAD, 0},
> +	{I2C5_SCL_GPIOC_89_PCONF0, I2C5_SCL_GPIOC_89_PAD, 0},
> +	{I2C6_SDA_GPIOC_90_PCONF0, I2C6_SDA_GPIOC_90_PAD, 0},
> +	{I2C6_SCL_GPIOC_91_PCONF0, I2C6_SCL_GPIOC_91_PAD, 0},
> +	{I2C_NFC_SDA_GPIOC_92_PCONF0, I2C_NFC_SDA_GPIOC_92_PAD, 0},
> +	{I2C_NFC_SCL_GPIOC_93_PCONF0, I2C_NFC_SCL_GPIOC_93_PAD, 0},
> +	{PWM0_GPIOC_94_PCONF0, PWM0_GPIOC_94_PAD, 0},
> +	{PWM1_GPIOC_95_PCONF0, PWM1_GPIOC_95_PAD, 0},
> +	{PLT_CLK0_GPIOC_96_PCONF0, PLT_CLK0_GPIOC_96_PAD, 0},
> +	{PLT_CLK1_GPIOC_97_PCONF0, PLT_CLK1_GPIOC_97_PAD, 0},
> +	{PLT_CLK2_GPIOC_98_PCONF0, PLT_CLK2_GPIOC_98_PAD, 0},
> +	{PLT_CLK3_GPIOC_99_PCONF0, PLT_CLK3_GPIOC_99_PAD, 0},
> +	{PLT_CLK4_GPIOC_100_PCONF0, PLT_CLK4_GPIOC_100_PAD, 0},
> +	{PLT_CLK5_GPIOC_101_PCONF0, PLT_CLK5_GPIOC_101_PAD, 0},
> +
> +	{GPIO_SUS0_GPIO_SUS0_PCONF0, GPIO_SUS0_GPIO_SUS0_PAD, 0},
> +	{GPIO_SUS1_GPIO_SUS1_PCONF0, GPIO_SUS1_GPIO_SUS1_PAD, 0},
> +	{GPIO_SUS2_GPIO_SUS2_PCONF0, GPIO_SUS2_GPIO_SUS2_PAD, 0},
> +	{GPIO_SUS3_GPIO_SUS3_PCONF0, GPIO_SUS3_GPIO_SUS3_PAD, 0},
> +	{GPIO_SUS4_GPIO_SUS4_PCONF0, GPIO_SUS4_GPIO_SUS4_PAD, 0},
> +	{GPIO_SUS5_GPIO_SUS5_PCONF0, GPIO_SUS5_GPIO_SUS5_PAD, 0},
> +	{GPIO_SUS6_GPIO_SUS6_PCONF0, GPIO_SUS6_GPIO_SUS6_PAD, 0},
> +	{GPIO_SUS7_GPIO_SUS7_PCONF0, GPIO_SUS7_GPIO_SUS7_PAD, 0},
> +	{SEC_GPIO_SUS8_GPIO_SUS8_PCONF0, SEC_GPIO_SUS8_GPIO_SUS8_PAD, 0},
> +	{SEC_GPIO_SUS9_GPIO_SUS9_PCONF0, SEC_GPIO_SUS9_GPIO_SUS9_PAD, 0},
> +	{SEC_GPIO_SUS10_GPIO_SUS10_PCONF0, SEC_GPIO_SUS10_GPIO_SUS10_PAD, 0},
> +	{SUSPWRDNACK_GPIOS_11_PCONF0, SUSPWRDNACK_GPIOS_11_PAD, 0},
> +	{PMU_SUSCLK_GPIOS_12_PCONF0, PMU_SUSCLK_GPIOS_12_PAD, 0},
> +	{PMU_SLP_S0IX_B_GPIOS_13_PCONF0, PMU_SLP_S0IX_B_GPIOS_13_PAD, 0},
> +	{PMU_SLP_LAN_B_GPIOS_14_PCONF0, PMU_SLP_LAN_B_GPIOS_14_PAD, 0},
> +	{PMU_WAKE_B_GPIOS_15_PCONF0, PMU_WAKE_B_GPIOS_15_PAD, 0},
> +	{PMU_PWRBTN_B_GPIOS_16_PCONF0, PMU_PWRBTN_B_GPIOS_16_PAD, 0},
> +	{PMU_WAKE_LAN_B_GPIOS_17_PCONF0, PMU_WAKE_LAN_B_GPIOS_17_PAD, 0},
> +	{SUS_STAT_B_GPIOS_18_PCONF0, SUS_STAT_B_GPIOS_18_PAD, 0},
> +	{USB_OC0_B_GPIOS_19_PCONF0, USB_OC0_B_GPIOS_19_PAD, 0},
> +	{USB_OC1_B_GPIOS_20_PCONF0, USB_OC1_B_GPIOS_20_PAD, 0},
> +	{SPI_CS1_B_GPIOS_21_PCONF0, SPI_CS1_B_GPIOS_21_PAD, 0},
> +	{GPIO_DFX0_GPIOS_22_PCONF0, GPIO_DFX0_GPIOS_22_PAD, 0},
> +	{GPIO_DFX1_GPIOS_23_PCONF0, GPIO_DFX1_GPIOS_23_PAD, 0},
> +	{GPIO_DFX2_GPIOS_24_PCONF0, GPIO_DFX2_GPIOS_24_PAD, 0},
> +	{GPIO_DFX3_GPIOS_25_PCONF0, GPIO_DFX3_GPIOS_25_PAD, 0},
> +	{GPIO_DFX4_GPIOS_26_PCONF0, GPIO_DFX4_GPIOS_26_PAD, 0},
> +	{GPIO_DFX5_GPIOS_27_PCONF0, GPIO_DFX5_GPIOS_27_PAD, 0},
> +	{GPIO_DFX6_GPIOS_28_PCONF0, GPIO_DFX6_GPIOS_28_PAD, 0},
> +	{GPIO_DFX7_GPIOS_29_PCONF0, GPIO_DFX7_GPIOS_29_PAD, 0},
> +	{GPIO_DFX8_GPIOS_30_PCONF0, GPIO_DFX8_GPIOS_30_PAD, 0},
> +	{USB_ULPI_0_CLK_GPIOS_31_PCONF0, USB_ULPI_0_CLK_GPIOS_31_PAD, 0},
> +	{USB_ULPI_0_DATA0_GPIOS_32_PCONF0, USB_ULPI_0_DATA0_GPIOS_32_PAD, 0},
> +	{USB_ULPI_0_DATA1_GPIOS_33_PCONF0, USB_ULPI_0_DATA1_GPIOS_33_PAD, 0},
> +	{USB_ULPI_0_DATA2_GPIOS_34_PCONF0, USB_ULPI_0_DATA2_GPIOS_34_PAD, 0},
> +	{USB_ULPI_0_DATA3_GPIOS_35_PCONF0, USB_ULPI_0_DATA3_GPIOS_35_PAD, 0},
> +	{USB_ULPI_0_DATA4_GPIOS_36_PCONF0, USB_ULPI_0_DATA4_GPIOS_36_PAD, 0},
> +	{USB_ULPI_0_DATA5_GPIOS_37_PCONF0, USB_ULPI_0_DATA5_GPIOS_37_PAD, 0},
> +	{USB_ULPI_0_DATA6_GPIOS_38_PCONF0, USB_ULPI_0_DATA6_GPIOS_38_PAD, 0},
> +	{USB_ULPI_0_DATA7_GPIOS_39_PCONF0, USB_ULPI_0_DATA7_GPIOS_39_PAD, 0},
> +	{USB_ULPI_0_DIR_GPIOS_40_PCONF0, USB_ULPI_0_DIR_GPIOS_40_PAD, 0},
> +	{USB_ULPI_0_NXT_GPIOS_41_PCONF0, USB_ULPI_0_NXT_GPIOS_41_PAD, 0},
> +	{USB_ULPI_0_STP_GPIOS_42_PCONF0, USB_ULPI_0_STP_GPIOS_42_PAD, 0},
> +	{USB_ULPI_0_REFCLK_GPIOS_43_PCONF0, USB_ULPI_0_REFCLK_GPIOS_43_PAD, 0}
>  };
>  
>  static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
> @@ -259,14 +422,42 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>  	u8 gpio, action;
>  	u16 function, pad;
>  	u32 val;
> +	u8 block;
>  	struct drm_device *dev = intel_dsi->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> +	DRM_DEBUG_DRIVER("MIPI: executing gpio element\n");
> +
> +	/*
> +	 * Skipping the first byte as it is of no
> +	 * interest for android in new version
> +	 */
> +	if (dev_priv->vbt.dsi.seq_version >= 3)
> +		data++;
> +
>  	gpio = *data++;
>  
>  	/* pull up/down */
>  	action = *data++;
>  
> +	if (dev_priv->vbt.dsi.seq_version >= 3) {
> +		if (gpio <= MAX_GPIO_NUM_NC) {
> +			DRM_DEBUG_DRIVER("GPIO is in the north Block\n");
> +			block = IOSF_PORT_GPIO_NC;
> +		} else if (gpio > MAX_GPIO_NUM_NC && gpio <= MAX_GPIO_NUM_SC) {
> +			DRM_DEBUG_DRIVER("GPIO is in the south Block\n");
> +			block = IOSF_PORT_GPIO_SC;
> +		} else if (gpio > MAX_GPIO_NUM_SC && gpio <= MAX_GPIO_NUM) {
> +			DRM_DEBUG_DRIVER("GPIO is in the SUS Block\n");
> +			block = IOSF_PORT_GPIO_SUS;
> +		} else {
> +			DRM_ERROR("GPIO number is not present in the table\n");
> +			return NULL;
> +		}
> +	} else {
> +		block = IOSF_PORT_GPIO_NC;
> +	}
> +
>  	function = gtable[gpio].function_reg;
>  	pad = gtable[gpio].pad_reg;
>  
> @@ -274,14 +465,14 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>  	if (!gtable[gpio].init) {
>  		/* program the function */
>  		/* FIXME: remove constant below */
> -		vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);
> +		vlv_gpio_write(dev_priv, block, function, 0x2000CC00);
>  		gtable[gpio].init = 1;
>  	}
>  
>  	val = 0x4 | action;
>  
>  	/* pull up/down */
> -	vlv_gpio_nc_write(dev_priv, pad, val);
> +	vlv_gpio_write(dev_priv, block, pad, val);
>  	mutex_unlock(&dev_priv->sb_lock);
>  
>  	return data;
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index 8831fc5..3e0cbe6 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -129,17 +129,18 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
>  	return val;
>  }
>  
> -u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
> +u32 vlv_gpio_read(struct drm_i915_private *dev_priv, u8 core_offset, u32 reg)
>  {
>  	u32 val = 0;
> -	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
> +	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), core_offset,
>  			SB_CRRDDA_NP, reg, &val);
>  	return val;
>  }
>  
> -void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> +void vlv_gpio_write(struct drm_i915_private *dev_priv, u8 core_offset,
> +				u32 reg, u32 val)
>  {
> -	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
> +	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), core_offset,
>  			SB_CRWRDA_NP, reg, &val);
>  }
>  
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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