[PATCH v2 0/6] drm/intel: guest i915 changes for Broadwell to run inside VM with Intel GVT-g

[PATCH v2 0/6] drm/intel: guest i915 changes for Broadwell to run inside VM with Intel GVT-g

[Zhiyuan Lv]

I915 kernel driver can now work inside a virtual machine on Haswell
with Intel GVT-g. In order to do the same thing on Broadwell, there
are some extra changes needed. The two main things are to support the
more complicated PPGTT page table structure and EXECLIST contexts.
GVT-g will perform shadow PPGTT, which requires guest driver to
explicitly notify host device model the life cycle of PPGTT page
tables.

The first patch added some restrictions to drivers in virtualization
scenario to make the shadow work easier. It is patch is based on
Mika's earlier one, and we use it for vgpu only. The fifth patch is
the implementation of the PPGTT notification.

v2:
- Rebase to latest drm-intel-next-queued
- Not to pin/unpin lr contexts and not to send notification for them (Chris)
- Address review comments from reviewers (noted in patches)


Zhiyuan Lv (6):
  drm/i915: preallocate pdps for 32 bit vgpu
  drm/i915: Enable full ppgtt for vgpu on Broadwell
  drm/i915: Always enable execlists on BDW for vgpu
  drm/i915: Update PV INFO page definition for Intel GVT-g
  drm/i915: guest i915 notification for Intel GVT-g
  drm/i915: Allow Broadwell guest with Intel GVT-g

 drivers/gpu/drm/i915/i915_gem_context.c |  7 +++
 drivers/gpu/drm/i915/i915_gem_gtt.c     | 78 ++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_vgpu.c        |  2 +-
 drivers/gpu/drm/i915/i915_vgpu.h        | 36 ++++++++++++++-
 drivers/gpu/drm/i915/intel_lrc.c        |  9 +++-
 5 files changed, 126 insertions(+), 6 deletions(-)

-- 
1.9.1

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[PATCH v2 1/6] drm/i915: preallocate pdps for 32 bit vgpu

[Zhiyuan Lv]

This is based on Mika Kuoppala's patch below:
http://article.gmane.org/gmane.comp.freedesktop.xorg.drivers.intel/61104/match=workaround+hw+preload

The patch will preallocate the page directories for 32-bit PPGTT when
i915 runs inside a virtual machine with Intel GVT-g. With this change,
the root pointers in EXECLIST context will always keep the same.

The change is needed for vGPU because Intel GVT-g will do page table
shadowing, and needs to track all the page table changes from guest
i915 driver. However, if guest PPGTT is modified through GPU commands
like LRI, it is not possible to trap the operations in the right time,
so it will be hard to make shadow PPGTT to work correctly.

Shadow PPGTT could be much simpler with this change. Meanwhile
hypervisor could simply prohibit any attempt of PPGTT modification
through GPU command for security.

The function gen8_preallocate_top_level_pdps() in the patch is from
Mika, with only one change to set "used_pdpes" to avoid duplicated
allocation later.

Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Dave Gordon <david.s.gordon@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Zhiyuan Lv <zhiyuan.lv@intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 33 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_lrc.c    |  3 ++-
 2 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4a76807..ed10e77 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1441,6 +1441,33 @@ static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
 	}
 }
 
+static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt)
+{
+	unsigned long *new_page_dirs, **new_page_tables;
+	uint32_t pdpes = I915_PDPES_PER_PDP(dev);
+	int ret;
+
+	/* We allocate temp bitmap for page tables for no gain
+	 * but as this is for init only, lets keep the things simple
+	 */
+	ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
+	if (ret)
+		return ret;
+
+	/* Allocate for all pdps regardless of how the ppgtt
+	 * was defined.
+	 */
+	ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp,
+						0, 1ULL << 32,
+						new_page_dirs);
+	if (!ret)
+		*ppgtt->pdp.used_pdpes = *new_page_dirs;
+
+	free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
+
+	return ret;
+}
+
 /*
  * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
  * with a net effect resembling a 2-level page table in normal x86 terms. Each
@@ -1484,6 +1511,12 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 		trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base,
 							      0, 0,
 							      GEN8_PML4E_SHIFT);
+
+		if (intel_vgpu_active(ppgtt->base.dev)) {
+			ret = gen8_preallocate_top_level_pdps(ppgtt);
+			if (ret)
+				goto free_scratch;
+		}
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 1af84c5..258af9b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1540,7 +1540,8 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
 	 * not needed in 48-bit.*/
 	if (req->ctx->ppgtt &&
 	    (intel_ring_flag(req->ring) & req->ctx->ppgtt->pd_dirty_rings)) {
-		if (!USES_FULL_48BIT_PPGTT(req->i915)) {
+		if (!USES_FULL_48BIT_PPGTT(req->i915) &&
+		    !intel_vgpu_active(req->i915->dev)) {
 			ret = intel_logical_ring_emit_pdps(req);
 			if (ret)
 				return ret;
-- 
1.9.1

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[PATCH v2 2/6] drm/i915: Enable full ppgtt for vgpu on Broadwell

[Zhiyuan Lv]

The full ppgtt is supported now in Intel GVT-g device model. Broadwell
is allowed to use it in virtual machines.

v2:
- Keep backward compatibility on HSW with old device model (daniel)

Signed-off-by: Zhiyuan Lv <zhiyuan.lv@intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ed10e77..56cc8e8 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -108,8 +108,8 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
 	has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
 	has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
 
-	if (intel_vgpu_active(dev))
-		has_full_ppgtt = false; /* emulation is too hard */
+	if (intel_vgpu_active(dev) && (IS_HASWELL(dev)))
+		has_full_ppgtt = false;
 
 	/*
 	 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
-- 
1.9.1

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Re: [PATCH v2 2/6] drm/i915: Enable full ppgtt for vgpu on Broadwell

[Joonas Lahtinen]

On pe, 2015-08-28 at 15:41 +0800, Zhiyuan Lv wrote:
> The full ppgtt is supported now in Intel GVT-g device model.
> Broadwell
> is allowed to use it in virtual machines.
> 
> v2:
> - Keep backward compatibility on HSW with old device model (daniel)
> 
> Signed-off-by: Zhiyuan Lv <zhiyuan.lv@intel.com>
> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

It's a good idea to add the version reviewed after Reviewed-by, when
adding a new revision. This is not to make it look like the new
revision had already been reviewed too.

I this case:

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v1)

Would have been appropriate.

But you can now leave it as it is, as this patch seems fine, too. Maybe
could still add a comment in the code what makes Haswell special.

Regards, Joonas

> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index ed10e77..56cc8e8 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -108,8 +108,8 @@ static int sanitize_enable_ppgtt(struct
> drm_device *dev, int enable_ppgtt)
>  	has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
>  	has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
>  
> -	if (intel_vgpu_active(dev))
> -		has_full_ppgtt = false; /* emulation is too hard */
> +	if (intel_vgpu_active(dev) && (IS_HASWELL(dev)))
> +		has_full_ppgtt = false;
>  
>  	/*
>  	 * We don't allow disabling PPGTT for gen9+ as it's a
> requirement for
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Re: [PATCH v2 2/6] drm/i915: Enable full ppgtt for vgpu on Broadwell

[Daniel Vetter]

On Mon, Aug 31, 2015 at 03:55:58PM +0300, Joonas Lahtinen wrote:
> On pe, 2015-08-28 at 15:41 +0800, Zhiyuan Lv wrote:
> > The full ppgtt is supported now in Intel GVT-g device model.
> > Broadwell
> > is allowed to use it in virtual machines.
> > 
> > v2:
> > - Keep backward compatibility on HSW with old device model (daniel)
> > 
> > Signed-off-by: Zhiyuan Lv <zhiyuan.lv@intel.com>
> > Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> > Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> 
> It's a good idea to add the version reviewed after Reviewed-by, when
> adding a new revision. This is not to make it look like the new
> revision had already been reviewed too.
> 
> I this case:
> 
> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v1)
> 
> Would have been appropriate.
> 
> But you can now leave it as it is, as this patch seems fine, too. Maybe
> could still add a comment in the code what makes Haswell special.
> 
> Regards, Joonas
> 
> > ---
> >  drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > index ed10e77..56cc8e8 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > @@ -108,8 +108,8 @@ static int sanitize_enable_ppgtt(struct
> > drm_device *dev, int enable_ppgtt)
> >  	has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
> >  	has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
> >  
> > -	if (intel_vgpu_active(dev))
> > -		has_full_ppgtt = false; /* emulation is too hard */
> > +	if (intel_vgpu_active(dev) && (IS_HASWELL(dev)))
> > +		has_full_ppgtt = false;

I'd say the real check here should be for INTEL_INFO(dev)->gen < 8. Only
checking for hsw is a bit confusing since then people wonder why hsw is
special. But the only reason is that vgpu isn't supported on pre-hsw.

Using the gen check instead will make it clear that this is a generic
issue with pre-gen8 hw (no execlists) and imo be less confusing. Maybe
even add a comment like:

	/* virtualizing ppgtt with execlists is too hard */
> >  
> >  	/*
> >  	 * We don't allow disabling PPGTT for gen9+ as it's a
> > requirement for
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[PATCH v2 3/6] drm/i915: Always enable execlists on BDW for vgpu

[Zhiyuan Lv]

Broadwell hardware supports both ring buffer mode and execlist mode.
When i915 runs inside a VM with Intel GVT-g, we allow execlist mode
only.

The main reason of EXECLIST only is that GVT-g does not support the
dynamic mode switch between ring buffer mode and execlist mode when
running multiple virtual machines.

v2:
- Adjust the position of vgpu check in sanitize function (Joonas)
- Add vgpu error check in context initialization. (Joonas, Daniel)

Signed-off-by: Zhiyuan Lv <zhiyuan.lv@intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_context.c | 7 +++++++
 drivers/gpu/drm/i915/intel_lrc.c        | 6 ++++++
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 8e893b3..74aa0c9 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -332,6 +332,13 @@ int i915_gem_context_init(struct drm_device *dev)
 	if (WARN_ON(dev_priv->ring[RCS].default_context))
 		return 0;
 
+	if (intel_vgpu_active(dev) && HAS_LOGICAL_RING_CONTEXTS(dev)) {
+		if (!i915.enable_execlists) {
+			DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
+			return -EINVAL;
+		}
+	}
+
 	if (i915.enable_execlists) {
 		/* NB: intentionally left blank. We will allocate our own
 		 * backing objects as we need them, thank you very much */
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 258af9b..e9520af 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -236,6 +236,12 @@ int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists
 {
 	WARN_ON(i915.enable_ppgtt == -1);
 
+	/* On platforms with execlist available, vGPU will only
+	 * support execlist mode, no ring buffer mode.
+	 */
+	if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev))
+		return 1;
+
 	if (INTEL_INFO(dev)->gen >= 9)
 		return 1;
 
-- 
1.9.1

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Re: [PATCH v2 3/6] drm/i915: Always enable execlists on BDW for vgpu

[Joonas Lahtinen]

On pe, 2015-08-28 at 15:41 +0800, Zhiyuan Lv wrote:
> Broadwell hardware supports both ring buffer mode and execlist mode.
> When i915 runs inside a VM with Intel GVT-g, we allow execlist mode
> only.
> 
> The main reason of EXECLIST only is that GVT-g does not support the
> dynamic mode switch between ring buffer mode and execlist mode when
> running multiple virtual machines.
> 
> v2:
> - Adjust the position of vgpu check in sanitize function (Joonas)
> - Add vgpu error check in context initialization. (Joonas, Daniel)
> 
> Signed-off-by: Zhiyuan Lv <zhiyuan.lv@intel.com>
> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_gem_context.c | 7 +++++++
>  drivers/gpu/drm/i915/intel_lrc.c        | 6 ++++++
>  2 files changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
> b/drivers/gpu/drm/i915/i915_gem_context.c
> index 8e893b3..74aa0c9 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -332,6 +332,13 @@ int i915_gem_context_init(struct drm_device
> *dev)
>  	if (WARN_ON(dev_priv->ring[RCS].default_context))
>  		return 0;
>  
> +	if (intel_vgpu_active(dev) &&
> HAS_LOGICAL_RING_CONTEXTS(dev)) {
> +		if (!i915.enable_execlists) {
> +			DRM_INFO("Only EXECLIST mode is supported in
> vgpu.\n");
> +			return -EINVAL;
> +		}
> +	}
> +
>  	if (i915.enable_execlists) {
>  		/* NB: intentionally left blank. We will allocate
> our own
>  		 * backing objects as we need them, thank you very
> much */
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 258af9b..e9520af 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -236,6 +236,12 @@ int intel_sanitize_enable_execlists(struct
> drm_device *dev, int enable_execlists
>  {
>  	WARN_ON(i915.enable_ppgtt == -1);
>  
> +	/* On platforms with execlist available, vGPU will only
> +	 * support execlist mode, no ring buffer mode.
> +	 */
> +	if (HAS_LOGICAL_RING_CONTEXTS(dev) &&
> intel_vgpu_active(dev))
> +		return 1;
> +
>  	if (INTEL_INFO(dev)->gen >= 9)
>  		return 1;
>  
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[PATCH v2 4/6] drm/i915: Update PV INFO page definition for Intel GVT-g

[Zhiyuan Lv]

Some more definitions in the PV info page are added. They are mainly
for the guest notification to Intel GVT-g device model. They are used
for Broadwell enabling.

The notification of PPGTT page table creation/destroy is to notify
GVT-g device model the life cycle of guest page tables. Then device
model will implement shadow page table for guests.

The notification of context create/destroy is optional. If it is used,
the device model will create/destroy shadow context corresponding to
the context's life cycle. Guest driver needs to make sure that the
context's LRCA and backing storage address unchanged. If it is not
used, the device model will perform the context shadow work in the
context scheduling time.


Signed-off-by: Zhiyuan Lv <zhiyuan.lv@intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_vgpu.h | 34 ++++++++++++++++++++++++++++++++--
 1 file changed, 32 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 97a88b5..21c97f4 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -40,6 +40,19 @@
 #define INTEL_VGT_IF_VERSION \
 	INTEL_VGT_IF_VERSION_ENCODE(VGT_VERSION_MAJOR, VGT_VERSION_MINOR)
 
+/*
+ * notifications from guest to vgpu device model
+ */
+enum vgt_g2v_type {
+	VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2,
+	VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY,
+	VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE,
+	VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
+	VGT_G2V_EXECLIST_CONTEXT_CREATE,
+	VGT_G2V_EXECLIST_CONTEXT_DESTROY,
+	VGT_G2V_MAX,
+};
+
 struct vgt_if {
 	uint64_t magic;		/* VGT_MAGIC */
 	uint16_t version_major;
@@ -70,11 +83,28 @@ struct vgt_if {
 	uint32_t rsv3[0x200 - 24];	/* pad to half page */
 	/*
 	 * The bottom half page is for response from Gfx driver to hypervisor.
-	 * Set to reserved fields temporarily by now.
 	 */
 	uint32_t rsv4;
 	uint32_t display_ready;	/* ready for display owner switch */
-	uint32_t rsv5[0x200 - 2];	/* pad to one page */
+
+	uint32_t rsv5[4];
+
+	uint32_t g2v_notify;
+	uint32_t rsv6[7];
+
+	uint32_t pdp0_lo;
+	uint32_t pdp0_hi;
+	uint32_t pdp1_lo;
+	uint32_t pdp1_hi;
+	uint32_t pdp2_lo;
+	uint32_t pdp2_hi;
+	uint32_t pdp3_lo;
+	uint32_t pdp3_hi;
+
+	uint32_t execlist_context_descriptor_lo;
+	uint32_t execlist_context_descriptor_hi;
+
+	uint32_t  rsv7[0x200 - 24];    /* pad to one page */
 } __packed;
 
 #define vgtif_reg(x) \
-- 
1.9.1

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[PATCH v2 5/6] drm/i915: guest i915 notification for Intel GVT-g

[Zhiyuan Lv]

When i915 drivers run inside a VM with Intel GVT-g, some explicit
notifications are needed from guest to host device model through PV
INFO page write. The notifications include:

	PPGTT create
	PPGTT destroy

They are used for the shadow implementation of PPGTT. Intel GVT-g
needs to write-protect the guest pages of PPGTT, and clear the write
protection when they end their life cycle.

v2:
- Use lower_32_bits()/upper_32_bits() for qword operations;
- Remove the notification of guest context creation/destroy;

Signed-off-by: Zhiyuan Lv <zhiyuan.lv@intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 41 +++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 56cc8e8..df60227 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -899,6 +899,41 @@ static int gen8_init_scratch(struct i915_address_space *vm)
 	return 0;
 }
 
+static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
+{
+	enum vgt_g2v_type msg;
+	struct drm_device *dev = ppgtt->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	unsigned int offset = vgtif_reg(pdp0_lo);
+	int i;
+
+	if (USES_FULL_48BIT_PPGTT(dev)) {
+		u64 daddr = px_dma(&ppgtt->pml4);
+
+		I915_WRITE(offset, lower_32_bits(daddr));
+		I915_WRITE(offset + 4, upper_32_bits(daddr));
+
+		msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
+				VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
+	} else {
+		for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
+			u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
+
+			I915_WRITE(offset, lower_32_bits(daddr));
+			I915_WRITE(offset + 4, upper_32_bits(daddr));
+
+			offset += 8;
+		}
+
+		msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
+				VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
+	}
+
+	I915_WRITE(vgtif_reg(g2v_notify), msg);
+
+	return 0;
+}
+
 static void gen8_free_scratch(struct i915_address_space *vm)
 {
 	struct drm_device *dev = vm->dev;
@@ -945,6 +980,9 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
 	struct i915_hw_ppgtt *ppgtt =
 		container_of(vm, struct i915_hw_ppgtt, base);
 
+	if (intel_vgpu_active(vm->dev))
+		gen8_ppgtt_notify_vgt(ppgtt, false);
+
 	if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
 		gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp);
 	else
@@ -1519,6 +1557,9 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 		}
 	}
 
+	if (intel_vgpu_active(ppgtt->base.dev))
+		gen8_ppgtt_notify_vgt(ppgtt, true);
+
 	return 0;
 
 free_scratch:
-- 
1.9.1

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Re: [PATCH v2 5/6] drm/i915: guest i915 notification for Intel GVT-g

[Joonas Lahtinen]

On pe, 2015-08-28 at 15:41 +0800, Zhiyuan Lv wrote:
> When i915 drivers run inside a VM with Intel GVT-g, some explicit
> notifications are needed from guest to host device model through PV
> INFO page write. The notifications include:
> 
> 	PPGTT create
> 	PPGTT destroy
> 
> They are used for the shadow implementation of PPGTT. Intel GVT-g
> needs to write-protect the guest pages of PPGTT, and clear the write
> protection when they end their life cycle.
> 
> v2:
> - Use lower_32_bits()/upper_32_bits() for qword operations;
> - Remove the notification of guest context creation/destroy;
> 
> Signed-off-by: Zhiyuan Lv <zhiyuan.lv@intel.com>
> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> 

Again, as there's really no formal spec of what the hypervisor expects
to see, that part is hard to comment on, so apart from that:

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

PS. Adding people who previously commented on the patch as CC, makes
the reviewing go much smoother (new revisions get picked up faster).

> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 41
> +++++++++++++++++++++++++++++++++++++
>  1 file changed, 41 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 56cc8e8..df60227 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -899,6 +899,41 @@ static int gen8_init_scratch(struct
> i915_address_space *vm)
>  	return 0;
>  }
>  
> +static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool
> create)
> +{
> +	enum vgt_g2v_type msg;
> +	struct drm_device *dev = ppgtt->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	unsigned int offset = vgtif_reg(pdp0_lo);
> +	int i;
> +
> +	if (USES_FULL_48BIT_PPGTT(dev)) {
> +		u64 daddr = px_dma(&ppgtt->pml4);
> +
> +		I915_WRITE(offset, lower_32_bits(daddr));
> +		I915_WRITE(offset + 4, upper_32_bits(daddr));
> +
> +		msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
> +				VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY)
> ;
> +	} else {
> +		for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
> +			u64 daddr = i915_page_dir_dma_addr(ppgtt,
> i);
> +
> +			I915_WRITE(offset, lower_32_bits(daddr));
> +			I915_WRITE(offset + 4,
> upper_32_bits(daddr));
> +
> +			offset += 8;
> +		}
> +
> +		msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
> +				VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY)
> ;
> +	}
> +
> +	I915_WRITE(vgtif_reg(g2v_notify), msg);
> +
> +	return 0;
> +}
> +
>  static void gen8_free_scratch(struct i915_address_space *vm)
>  {
>  	struct drm_device *dev = vm->dev;
> @@ -945,6 +980,9 @@ static void gen8_ppgtt_cleanup(struct
> i915_address_space *vm)
>  	struct i915_hw_ppgtt *ppgtt =
>  		container_of(vm, struct i915_hw_ppgtt, base);
>  
> +	if (intel_vgpu_active(vm->dev))
> +		gen8_ppgtt_notify_vgt(ppgtt, false);
> +
>  	if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
>  		gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt
> ->pdp);
>  	else
> @@ -1519,6 +1557,9 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt
> *ppgtt)
>  		}
>  	}
>  
> +	if (intel_vgpu_active(ppgtt->base.dev))
> +		gen8_ppgtt_notify_vgt(ppgtt, true);
> +
>  	return 0;
>  
>  free_scratch:
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[PATCH v2 6/6] drm/i915: Allow Broadwell guest with Intel GVT-g

[Zhiyuan Lv]

I915 Broadwell guest driver is now supported to run inside a VM with
Intel GVT-g

v2:
- Introduce HAS_VGPU macro (Zhenyu Wang)

Signed-off-by: Zhiyuan Lv <zhiyuan.lv@intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_vgpu.c | 2 +-
 drivers/gpu/drm/i915/i915_vgpu.h | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 5eee75b..f98a979 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -66,7 +66,7 @@ void i915_check_vgpu(struct drm_device *dev)
 
 	BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
 
-	if (!IS_HASWELL(dev))
+	if (!HAS_VGPU(dev))
 		return;
 
 	magic = readq(dev_priv->regs + vgtif_reg(magic));
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 21c97f4..9a9eb57 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -114,6 +114,8 @@ struct vgt_if {
 #define VGT_DRV_DISPLAY_NOT_READY 0
 #define VGT_DRV_DISPLAY_READY     1  /* ready for display switch */
 
+#define HAS_VGPU(dev)	(IS_HASWELL(dev) || IS_BROADWELL(dev))
+
 extern void i915_check_vgpu(struct drm_device *dev);
 extern int intel_vgt_balloon(struct drm_device *dev);
 extern void intel_vgt_deballoon(void);
-- 
1.9.1

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Re: [PATCH v2 6/6] drm/i915: Allow Broadwell guest with Intel GVT-g

[Daniel Vetter]

On Fri, Aug 28, 2015 at 03:41:19PM +0800, Zhiyuan Lv wrote:
> I915 Broadwell guest driver is now supported to run inside a VM with
> Intel GVT-g
> 
> v2:
> - Introduce HAS_VGPU macro (Zhenyu Wang)
> 
> Signed-off-by: Zhiyuan Lv <zhiyuan.lv@intel.com>
> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

I'll hold of on this one for the polished version of patch 2, but all
others are merged to dinq.

Thanks, Daniel

> ---
>  drivers/gpu/drm/i915/i915_vgpu.c | 2 +-
>  drivers/gpu/drm/i915/i915_vgpu.h | 2 ++
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
> index 5eee75b..f98a979 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.c
> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> @@ -66,7 +66,7 @@ void i915_check_vgpu(struct drm_device *dev)
>  
>  	BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
>  
> -	if (!IS_HASWELL(dev))
> +	if (!HAS_VGPU(dev))
>  		return;
>  
>  	magic = readq(dev_priv->regs + vgtif_reg(magic));
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
> index 21c97f4..9a9eb57 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.h
> +++ b/drivers/gpu/drm/i915/i915_vgpu.h
> @@ -114,6 +114,8 @@ struct vgt_if {
>  #define VGT_DRV_DISPLAY_NOT_READY 0
>  #define VGT_DRV_DISPLAY_READY     1  /* ready for display switch */
>  
> +#define HAS_VGPU(dev)	(IS_HASWELL(dev) || IS_BROADWELL(dev))
> +
>  extern void i915_check_vgpu(struct drm_device *dev);
>  extern int intel_vgt_balloon(struct drm_device *dev);
>  extern void intel_vgt_deballoon(void);
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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