[BXT DMC PATCHES 0/3] Extended dmc support for broxton.

[BXT DMC PATCHES 0/3] Extended dmc support for broxton.

[Animesh Manna]

This patches will extend the support for broxton.

Earlier these patches are sent part of "Redesign of dmc firmware loading"
patch series.
http://lists.freedesktop.org/archives/intel-gfx/2015-July/072331.html

To make it simple, bxt specific patches are seperated out and based on
review comments from Sunil, minor changes are done.

Animesh Manna (3):
  drm/i915/bxt: Path added of dmc firmware ver1 for BXT.
  drm/i915/bxt: Modified HAS_CSR, added support for BXT
  drm/i915/bxt: Stepping info added for bxt.

 drivers/gpu/drm/i915/i915_drv.h  |  2 +-
 drivers/gpu/drm/i915/intel_csr.c | 15 +++++++++++++++
 2 files changed, 16 insertions(+), 1 deletion(-)

-- 
2.0.2

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[BXT DMC PATCHES 1/3] drm/i915/bxt: Path added of dmc firmware ver1 for BXT.

[Animesh Manna]

Broxton also has dmc to manage low-power display engine state.
Path of the firmware added in intel_csr.c.

Naming convention followed as <platform>_dmc_<api-version>.bin

v1: Initial version.

v2: Commit description added based on review comment from Sunil.

Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/intel_csr.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 18a0670..c89b9ce 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -42,8 +42,10 @@
  */
 
 #define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
+#define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
 
 MODULE_FIRMWARE(I915_CSR_SKL);
+MODULE_FIRMWARE(I915_CSR_BXT);
 
 struct intel_css_header {
 	/* 0x09 for DMC */
@@ -372,6 +374,8 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 
 	if (IS_SKYLAKE(dev_priv))
 		csr->fw_path = I915_CSR_SKL;
+	else if (IS_BROXTON(dev_priv))
+		csr->fw_path = I915_CSR_BXT;
 	else {
 		DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
 		return;
-- 
2.0.2

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[BXT DMC PATCHES 2/3] drm/i915/bxt: Modified HAS_CSR, added support for BXT

[Animesh Manna]

Modified HAS_CSR macro defination which earlier only supported
for skl, now added support for BXT.

v1: Initial version.

v2: Instaed of skylake/broxton check added gen9 check alone based
on review comment from Sunil.

Cc: Vetter, Daniel <daniel.vetter@intel.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 773883d..c9a887f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2533,7 +2533,7 @@ struct drm_i915_cmd_table {
 #define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
 #define HAS_RC6p(dev)		(INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
 
-#define HAS_CSR(dev)	(IS_SKYLAKE(dev))
+#define HAS_CSR(dev)	(IS_GEN9(dev))
 
 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
 				    INTEL_INFO(dev)->gen >= 8)
-- 
2.0.2

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[BXT DMC PATCHES 3/3] drm/i915/bxt: Stepping info added for bxt.

[Animesh Manna]

Added stepping info in intel_csr.c which is required to extract
specific firmware from packaged dmc firmware.

Stepping info is aligned with current bspec info.

Cc: Vetter, Daniel <daniel.vetter@intel.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/intel_csr.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index c89b9ce..06b46b1 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -167,11 +167,19 @@ static const struct stepping_info skl_stepping_info[] = {
 	{'G', '0'}, {'H', '0'}, {'I', '0'}
 };
 
+static struct stepping_info bxt_stepping_info[] = {
+	{'A', '0'}, {'A', '1'}, {'A', '2'},
+	{'B', '0'}, {'B', '1'}, {'B', '2'}
+};
+
 static char intel_get_stepping(struct drm_device *dev)
 {
 	if (IS_SKYLAKE(dev) && (dev->pdev->revision <
 				ARRAY_SIZE(skl_stepping_info)))
 		return skl_stepping_info[dev->pdev->revision].stepping;
+	else if (IS_BROXTON(dev) && (dev->pdev->revision <
+				ARRAY_SIZE(bxt_stepping_info)))
+		return bxt_stepping_info[dev->pdev->revision].stepping;
 	else
 		return -ENODATA;
 }
@@ -181,6 +189,9 @@ static char intel_get_substepping(struct drm_device *dev)
 	if (IS_SKYLAKE(dev) && (dev->pdev->revision <
 				ARRAY_SIZE(skl_stepping_info)))
 		return skl_stepping_info[dev->pdev->revision].substepping;
+	else if (IS_BROXTON(dev) && (dev->pdev->revision <
+			ARRAY_SIZE(bxt_stepping_info)))
+		return bxt_stepping_info[dev->pdev->revision].substepping;
 	else
 		return -ENODATA;
 }
-- 
2.0.2

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Re: [BXT DMC PATCHES 1/3] drm/i915/bxt: Path added of dmc firmware ver1 for BXT.

[Vivi, Rodrigo]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


On Tue, 2015-08-04 at 22:02 +0530, Animesh Manna wrote:
> Broxton also has dmc to manage low-power display engine state.
> Path of the firmware added in intel_csr.c.
> 
> Naming convention followed as <platform>_dmc_<api-version>.bin
> 
> v1: Initial version.
> 
> v2: Commit description added based on review comment from Sunil.
> 
> Cc: Damien Lespiau <damien.lespiau@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Sunil Kamath <sunil.kamath@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_csr.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> index 18a0670..c89b9ce 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -42,8 +42,10 @@
>   */
>  
>  #define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
> +#define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
>  
>  MODULE_FIRMWARE(I915_CSR_SKL);
> +MODULE_FIRMWARE(I915_CSR_BXT);
>  
>  struct intel_css_header {
>  	/* 0x09 for DMC */
> @@ -372,6 +374,8 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
>  
>  	if (IS_SKYLAKE(dev_priv))
>  		csr->fw_path = I915_CSR_SKL;
> +	else if (IS_BROXTON(dev_priv))
> +		csr->fw_path = I915_CSR_BXT;
>  	else {
>  		DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
>  		return;

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Re: [BXT DMC PATCHES 0/3] Extended dmc support for broxton.

[Imre Deak]

On ti, 2015-08-04 at 22:02 +0530, Animesh Manna wrote:
> This patches will extend the support for broxton.
> 
> Earlier these patches are sent part of "Redesign of dmc firmware loading"
> patch series.
> http://lists.freedesktop.org/archives/intel-gfx/2015-July/072331.html
> 
> To make it simple, bxt specific patches are seperated out and based on
> review comments from Sunil, minor changes are done.
> 
> Animesh Manna (3):
>   drm/i915/bxt: Path added of dmc firmware ver1 for BXT.
>   drm/i915/bxt: Modified HAS_CSR, added support for BXT
>   drm/i915/bxt: Stepping info added for bxt.

Patch 3/3 needs rebasing, other than that patches 2-3 look ok:
Reviewed-by: Imre Deak <imre.deak@intel.com>

With Rodrigo's r-b on patch 1 all the patches in this patchset have an
r-b now.

> 
>  drivers/gpu/drm/i915/i915_drv.h  |  2 +-
>  drivers/gpu/drm/i915/intel_csr.c | 15 +++++++++++++++
>  2 files changed, 16 insertions(+), 1 deletion(-)
> 


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Re: [BXT DMC PATCHES 2/3] drm/i915/bxt: Modified HAS_CSR, added support for BXT

[Daniel Vetter]

On Tue, Aug 04, 2015 at 10:02:42PM +0530, Animesh Manna wrote:
> Modified HAS_CSR macro defination which earlier only supported
> for skl, now added support for BXT.
> 
> v1: Initial version.
> 
> v2: Instaed of skylake/broxton check added gen9 check alone based
> on review comment from Sunil.
> 
> Cc: Vetter, Daniel <daniel.vetter@intel.com>
> Cc: Damien Lespiau <damien.lespiau@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Sunil Kamath <sunil.kamath@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>

The feature-enabling patch should always be last, to avoid breaking
machines in the middle of your patch series. I've reordered them while
applying the entire patch series.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 773883d..c9a887f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2533,7 +2533,7 @@ struct drm_i915_cmd_table {
>  #define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
>  #define HAS_RC6p(dev)		(INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
>  
> -#define HAS_CSR(dev)	(IS_SKYLAKE(dev))
> +#define HAS_CSR(dev)	(IS_GEN9(dev))
>  
>  #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
>  				    INTEL_INFO(dev)->gen >= 8)
> -- 
> 2.0.2
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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