[PATCH] drm/i915: Reset dpll_hw_state when selecting a new pll on hsw

[Gabriel Feceoru <gabriel.feceoru@intel.com>]

Using 2 connectors (DVI and VGA) will cause wrpll to be set for
INTEL_OUTPUT_HDMI but never reset if switching to INTEL_OUTPUT_VGA

Supresses errors like these:
[drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.wrpll

Signed-off-by: Gabriel Feceoru <gabriel.feceoru@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 4823184..1e5001a 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1245,6 +1245,9 @@ hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
 {
 	int clock = crtc_state->port_clock;
 
+	memset(&crtc_state->dpll_hw_state, 0,
+	       sizeof(crtc_state->dpll_hw_state));
+
 	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
 		struct intel_shared_dpll *pll;
 		uint32_t val;
@@ -1256,9 +1259,6 @@ hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
 		      WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 		      WRPLL_DIVIDER_POST(p);
 
-		memset(&crtc_state->dpll_hw_state, 0,
-		       sizeof(crtc_state->dpll_hw_state));
-
 		crtc_state->dpll_hw_state.wrpll = val;
 
 		pll = intel_get_shared_dpll(intel_crtc, crtc_state);
-- 
1.9.1

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