Re: [PATCH 6/9] drm/i915: driver based PASID handling

From: David Woodhouse <dwmw2@infradead.org>
To: Jesse Barnes <jbarnes@virtuousgeek.org>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 6/9] drm/i915: driver based PASID handling
Date: Wed, 07 Oct 2015 14:00:16 +0100	[thread overview]
Message-ID: <1444222816.4674.322.camel@infradead.org> (raw)
In-Reply-To: <1441385943-11508-7-git-send-email-jbarnes@virtuousgeek.org>

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On Fri, 2015-09-04 at 09:59 -0700, Jesse Barnes wrote:
> +
> +       ret = handle_mm_fault(mm, vma, address,
> +                             desc.wr_req ? FAULT_FLAG_WRITE : 0);
> +       if (ret & VM_FAULT_ERROR) {
> +               gpu_mm_segv(tsk, address, SEGV_ACCERR); /* ? */
> +               goto out_unlock;
> +       }
> +

Hm, do you need to force the SEGV there, in what ought to be generic
IOMMU code?

Can you instead just let the fault handler return an appropriate
failure code to the IOMMU request queue and then deal with the
resulting error on the i915 device side?

That way, you should hopefully get to gracefully cope with reporting
errors for a specific *context*, rather than killing the whole process.

-- 
David Woodhouse                            Open Source Technology Centre
David.Woodhouse@intel.com                              Intel Corporation

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