Re: [DMC_REDESIGN_V2 05/14] drm/i915/gen9: Remove csr.state, csr_lock and related code.

[Imre Deak <imre.deak@intel.com>]

On ke, 2015-08-26 at 16:58 +0530, Animesh Manna wrote:
> From: Daniel Vetter <daniel.vetter@intel.com>
> 
> This removes two anti-patterns:
> - Locking shouldn't be used to synchronize with async work (of any
>   form, whether callbacks, workers or other threads). This is what the
>   mutex_lock/unlock seems to have been for in intel_csr_load_program.
>   Instead ordering should be ensured with the generic
>   wait_for_completion()/complete(). Or more specific functions
>   provided by the core kernel like e.g.
>   flush_work()/cancel_work_sync() in the case of synchronizing with a
>   work item.
> 
> - Don't invent own completion like the following code did with the
>   (already removed) wait_for(csr_load_status_get()) pattern - it's
>   really hard to get these right when you want them to be _really_
>   correct (and be fast) in all cases. Furthermore it's easier to read
>   code using the well-known primitives than new ones using
>   non-standard names.
> 
> Cc: Damien Lespiau <damien.lespiau@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Sunil Kamath <sunil.kamath@intel.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_dma.c         |  1 -
>  drivers/gpu/drm/i915/i915_drv.c         | 13 ++--------
>  drivers/gpu/drm/i915/i915_drv.h         | 10 -------
>  drivers/gpu/drm/i915/intel_csr.c        | 46 +--------------------------------
>  drivers/gpu/drm/i915/intel_drv.h        |  3 ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 17 ++----------
>  6 files changed, 5 insertions(+), 85 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 48b9792..aa3cdcf 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -839,7 +839,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
>  	spin_lock_init(&dev_priv->mmio_flip_lock);
>  	mutex_init(&dev_priv->sb_lock);
>  	mutex_init(&dev_priv->modeset_restore_lock);
> -	mutex_init(&dev_priv->csr_lock);
>  
>  	intel_pm_setup(dev);
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index fa66162..1ddf3a9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1013,19 +1013,11 @@ static int i915_pm_resume(struct device *dev)
>  
>  static int skl_suspend_complete(struct drm_i915_private *dev_priv)
>  {
> -	enum csr_state state;
>  	/* Enabling DC6 is not a hard requirement to enter runtime D3 */
>  
>  	skl_uninit_cdclk(dev_priv);
>  
> -	/* TODO: wait for a completion event or
> -	 * similar here instead of busy
> -	 * waiting using wait_for function.
> -	 */
> -	wait_for((state = intel_csr_load_status_get(dev_priv)) !=
> -			FW_UNINITIALIZED, 1000);
> -	if (state == FW_LOADED)
> -		skl_enable_dc6(dev_priv);
> +	skl_enable_dc6(dev_priv);

Here the firmware may not be loaded yet during system suspend. Since
patch 11/14 moves the firmware loading to a work item, we could flush
that work in i915_drm_suspend() and check here if csr->dmc_payload is
set before enabling DC6. (and reorder this patch after patch 11).

>  
>  	return 0;
>  }
> @@ -1073,8 +1065,7 @@ static int skl_resume_prepare(struct drm_i915_private *dev_priv)
>  {
>  	struct drm_device *dev = dev_priv->dev;
>  
> -	if (intel_csr_load_status_get(dev_priv) == FW_LOADED)
> -		skl_disable_dc6(dev_priv);
> +	skl_disable_dc6(dev_priv);

As above we should check here for csr->dmc_payload.

>  	skl_init_cdclk(dev_priv);
>  	intel_csr_load_program(dev);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e0f3f05..9f01c72 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -736,12 +736,6 @@ struct intel_uncore {
>  #define for_each_fw_domain(domain__, dev_priv__, i__) \
>  	for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
>  
> -enum csr_state {
> -	FW_UNINITIALIZED = 0,
> -	FW_LOADED,
> -	FW_FAILED
> -};
> -
>  struct intel_csr {
>  	const char *fw_path;
>  	uint32_t *dmc_payload;
> @@ -749,7 +743,6 @@ struct intel_csr {
>  	uint32_t mmio_count;
>  	uint32_t mmioaddr[8];
>  	uint32_t mmiodata[8];
> -	enum csr_state state;
>  };
>  
>  #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
> @@ -1714,9 +1707,6 @@ struct drm_i915_private {
>  
>  	struct intel_csr csr;
>  
> -	/* Display CSR-related protection */
> -	struct mutex csr_lock;
> -
>  	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
>  
>  	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> index 9153764..ee2079b 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -184,40 +184,6 @@ static char intel_get_substepping(struct drm_device *dev)
>  }
>  
>  /**
> - * intel_csr_load_status_get() - to get firmware loading status.
> - * @dev_priv: i915 device.
> - *
> - * This function helps to get the firmware loading status.
> - *
> - * Return: Firmware loading status.
> - */
> -enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv)
> -{
> -	enum csr_state state;
> -
> -	mutex_lock(&dev_priv->csr_lock);
> -	state = dev_priv->csr.state;
> -	mutex_unlock(&dev_priv->csr_lock);
> -
> -	return state;
> -}
> -
> -/**
> - * intel_csr_load_status_set() - help to set firmware loading status.
> - * @dev_priv: i915 device.
> - * @state: enumeration of firmware loading status.
> - *
> - * Set the firmware loading status.
> - */
> -void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
> -			enum csr_state state)
> -{
> -	mutex_lock(&dev_priv->csr_lock);
> -	dev_priv->csr.state = state;
> -	mutex_unlock(&dev_priv->csr_lock);
> -}
> -
> -/**
>   * intel_csr_load_program() - write the firmware from memory to register.
>   * @dev: drm device.
>   *
> @@ -245,7 +211,6 @@ void intel_csr_load_program(struct drm_device *dev)
>  	if (I915_READ(CSR_PROGRAM_BASE))
>  		return;
>  
> -	mutex_lock(&dev_priv->csr_lock);
>  	fw_size = dev_priv->csr.dmc_fw_size;
>  	for (i = 0; i < fw_size; i++)
>  		I915_WRITE(CSR_PROGRAM_BASE + i * 4,
> @@ -255,9 +220,6 @@ void intel_csr_load_program(struct drm_device *dev)
>  		I915_WRITE(dev_priv->csr.mmioaddr[i],
>  			dev_priv->csr.mmiodata[i]);
>  	}
> -
> -	dev_priv->csr.state = FW_LOADED;
> -	mutex_unlock(&dev_priv->csr_lock);
>  }
>  
>  static void finish_csr_load(const struct firmware *fw, void *context)
> @@ -378,8 +340,6 @@ static void finish_csr_load(const struct firmware *fw, void *context)
>  out:
>  	if (fw_loaded || IS_BROXTON(dev))
>  		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
> -	else
> -		intel_csr_load_status_set(dev_priv, FW_FAILED);
>  
>  	release_firmware(fw);
>  }
> @@ -404,7 +364,6 @@ void intel_csr_ucode_init(struct drm_device *dev)
>  		csr->fw_path = I915_CSR_SKL;
>  	else {
>  		DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
> -		intel_csr_load_status_set(dev_priv, FW_FAILED);
>  		return;
>  	}
>  
> @@ -421,10 +380,8 @@ void intel_csr_ucode_init(struct drm_device *dev)
>  				&dev_priv->dev->pdev->dev,
>  				GFP_KERNEL, dev_priv,
>  				finish_csr_load);
> -	if (ret) {
> +	if (ret)
>  		i915_firmware_load_error_print(csr->fw_path, ret);
> -		intel_csr_load_status_set(dev_priv, FW_FAILED);
> -	}
>  }
>  
>  /**
> @@ -441,7 +398,6 @@ void intel_csr_ucode_fini(struct drm_device *dev)
>  	if (!HAS_CSR(dev))
>  		return;
>  
> -	intel_csr_load_status_set(dev_priv, FW_FAILED);
>  	kfree(dev_priv->csr.dmc_payload);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index c178ae8..a5e4b08 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1152,9 +1152,6 @@ u32 skl_plane_ctl_rotation(unsigned int rotation);
>  
>  /* intel_csr.c */
>  void intel_csr_ucode_init(struct drm_device *dev);
> -enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv);
> -void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
> -					enum csr_state state);
>  void intel_csr_load_program(struct drm_device *dev);
>  void intel_csr_ucode_fini(struct drm_device *dev);
>  
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 71832dc..3ffebb7 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -661,8 +661,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
>  	} else {
>  		if (enable_requested) {
>  			if (IS_SKYLAKE(dev) &&
> -				(power_well->data == SKL_DISP_PW_1) &&
> -				(intel_csr_load_status_get(dev_priv) == FW_LOADED))
> +				(power_well->data == SKL_DISP_PW_1))
>  				DRM_DEBUG_KMS("Not Disabling PW1, dmc will handle\n");
>  			else {
>  				I915_WRITE(HSW_PWR_WELL_DRIVER,	tmp & ~req_mask);
> @@ -671,20 +670,8 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
>  			}
>  
>  			if (GEN9_ENABLE_DC5(dev) &&
> -				power_well->data == SKL_DISP_PW_2) {
> -				enum csr_state state;
> -				/* TODO: wait for a completion event or
> -				 * similar here instead of busy
> -				 * waiting using wait_for function.
> -				 */
> -				wait_for((state = intel_csr_load_status_get(dev_priv)) !=
> -						FW_UNINITIALIZED, 1000);
> -				if (state != FW_LOADED)
> -					DRM_ERROR("CSR firmware not ready (%d)\n",
> -							state);
> -				else
> +				power_well->data == SKL_DISP_PW_2)
>  					gen9_enable_dc5(dev_priv);
> -			}
>  		}
>  	}
>  


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