[PATCH 21/26] drm/i915: check for FBC planes in the same place as the pipes

Paulo Zanoni
2015-10-27T16:51:10Z

This moves the pre-gen4 check from update() to enable(). The HAS_DDI
in the original code is not needed since only gen 2/3 have the plane
swapping code.

v2: Rebase.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_fbc.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index a9f133a..01807c5 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -570,6 +570,9 @@ static bool crtc_can_fbc(struct intel_crtc *crtc)
if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
return false;

+ if (INTEL_INFO(dev_priv)->gen < 4 && crtc->plane != PLANE_A)
+ return false;
+
return true;
}

@@ -849,12 +852,6 @@ static void __intel_fbc_update(struct intel_crtc *crtc)
goto out_disable;
}

- if ((INTEL_INFO(dev_priv)->gen < 4 || HAS_DDI(dev_priv)) &&
- crtc->plane != PLANE_A) {
- set_no_fbc_reason(dev_priv, "FBC unsupported on plane");
- goto out_disable;
- }
-
/* The use of a CPU fence is mandatory in order to detect writes
* by the CPU to the scanout and trigger updates to the FBC.
*/