Re: [PATCH 4/7] drm/i915/skl: Expose DC5/DC6 entry counts

[Imre Deak <imre.deak@intel.com>]

On ti, 2015-10-27 at 14:47 +0200, Mika Kuoppala wrote:
> From: Damien Lespiau <damien.lespiau@intel.com>
> 
> The CSR firmware expose two counters, handy to check if we are indeed
> entering DC5/DC6.
> 
> v2: Rebase
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> (v1)
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 7 +++++++
>  drivers/gpu/drm/i915/i915_reg.h     | 4 ++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 2f53cb1..d8e9bc8 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2806,6 +2806,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>  	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
>  		   CSR_VERSION_MINOR(csr->version));
>  
> +	if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
> +		seq_printf(m, "DC3 -> DC5 count: %d\n",
> +			   I915_READ(SKL_CSR_DC3_DC5_COUNT));
> +		seq_printf(m, "DC5 -> DC6 count: %d\n",
> +			   I915_READ(SKL_CSR_DC5_DC6_COUNT));
> +	}
> +

These registers return all 0xFF without an RPM ref.

>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8942532..bf9bddd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5696,6 +5696,10 @@ enum skl_disp_power_wells {
>  #define GAMMA_MODE_MODE_12BIT	(2 << 0)
>  #define GAMMA_MODE_MODE_SPLIT	(3 << 0)
>  
> +/* DMC/CSR */
> +#define SKL_CSR_DC3_DC5_COUNT	0x80030
> +#define SKL_CSR_DC5_DC6_COUNT	0x8002C
> +
>  /* interrupts */
>  #define DE_MASTER_IRQ_CONTROL   (1 << 31)
>  #define DE_SPRITEB_FLIP_DONE    (1 << 29)


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