[PATCH 1/7] drm/i915/skl: Store and print the DMC firmware version we load

[PATCH 1/7] drm/i915/skl: Store and print the DMC firmware version we load

[Mika Kuoppala]

From: Damien Lespiau <damien.lespiau@intel.com>

That can be handy later on to tell which DMC firmware version the user
has, by just looking at the dmesg.

v2: use DRM_DEBUG_DRIVER (Chris)
v3: use DRM_INFO (Marc Herbert)

Cc: Marc Herbert <marc.herbert@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  | 5 +++++
 drivers/gpu/drm/i915/intel_csr.c | 9 ++++++++-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b408ebf..0bee438 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -734,6 +734,10 @@ struct intel_uncore {
 #define for_each_fw_domain(domain__, dev_priv__, i__) \
 	for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
 
+#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
+#define CSR_VERSION_MAJOR(version)	((version) >> 16)
+#define CSR_VERSION_MINOR(version)	((version) & 0xffff)
+
 enum csr_state {
 	FW_UNINITIALIZED = 0,
 	FW_LOADED,
@@ -744,6 +748,7 @@ struct intel_csr {
 	const char *fw_path;
 	uint32_t *dmc_payload;
 	uint32_t dmc_fw_size;
+	uint32_t version;
 	uint32_t mmio_count;
 	uint32_t mmioaddr[8];
 	uint32_t mmiodata[8];
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 9e530a7..e620e85 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -321,6 +321,9 @@ static void finish_csr_load(const struct firmware *fw, void *context)
 			(css_header->header_len * 4));
 		goto out;
 	}
+
+	csr->version = css_header->version;
+
 	readcount += sizeof(struct intel_css_header);
 
 	/* Extract Package Header information*/
@@ -402,7 +405,11 @@ static void finish_csr_load(const struct firmware *fw, void *context)
 	intel_csr_load_program(dev);
 	fw_loaded = true;
 
-	DRM_DEBUG_KMS("Finished loading %s\n", dev_priv->csr.fw_path);
+	DRM_INFO("Finished loading %s (v%u.%u)\n",
+		 dev_priv->csr.fw_path,
+		 CSR_VERSION_MAJOR(csr->version),
+		 CSR_VERSION_MINOR(csr->version));
+
 out:
 	if (fw_loaded)
 		intel_runtime_pm_put(dev_priv);
-- 
2.5.0

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[PATCH 2/7] drm/i915/skl: Refuse to load outdated dmc firmware

[Mika Kuoppala]

There is known issue on GT interrupt delivery with DC6 and
firmwares <1.21. There is a suspicion that this causes
spurious gpu hangs on driver init and with some workloads,
as upgrading the firmware to 1.21 makes these problems
disappear.

As of now the current version included in distribution
firmware packages is very like to be 1.19. Play it safe and
refuse to load a firmware version that may affect gpu
side stability.

With < 1.23 there is a palette and dmc ram corruption issue
so blacklist anything below that.

v2: Refuse to load fw instead of notifying the user
v3: Rebase on header version changes
v4: Refuse to load anything less than 1.23
v5: Give enough information for user for finding correct fw (Chris)
v6: better url and formatting (Chris)
v7: move error log for each fail path (Mika)
    bail out earlier in load path (Imre)

Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Dave Gordon <david.s.gordon@intel.com>
Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
References: https://01.org/linuxgraphics/downloads/skldmcver121
References: https://01.org/linuxgraphics/downloads/skylake-dmc-1.23
Testcase: igt/gem_exec_nop
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_csr.c | 37 +++++++++++++++++++++++++++----------
 1 file changed, 27 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index e620e85..701c685 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -47,6 +47,9 @@
 MODULE_FIRMWARE(I915_CSR_SKL);
 MODULE_FIRMWARE(I915_CSR_BXT);
 
+#define SKL_REQUIRED_FW_MAJOR	1
+#define SKL_REQUIRED_FW_MINOR	23
+
 /*
 * SKL CSR registers for DC5 and DC6
 */
@@ -303,10 +306,8 @@ static void finish_csr_load(const struct firmware *fw, void *context)
 	uint32_t *dmc_payload;
 	bool fw_loaded = false;
 
-	if (!fw) {
-		i915_firmware_load_error_print(csr->fw_path, 0);
+	if (!fw)
 		goto out;
-	}
 
 	if ((stepping == -ENODATA) || (substepping == -ENODATA)) {
 		DRM_ERROR("Unknown stepping info, firmware loading failed\n");
@@ -324,6 +325,19 @@ static void finish_csr_load(const struct firmware *fw, void *context)
 
 	csr->version = css_header->version;
 
+	if (IS_SKYLAKE(dev) &&
+	    (CSR_VERSION_MAJOR(csr->version) < SKL_REQUIRED_FW_MAJOR ||
+	     CSR_VERSION_MINOR(csr->version) < SKL_REQUIRED_FW_MINOR)) {
+		DRM_INFO("Refusing to load old Skylake DMC firmware v%u.%u,"
+			 " please upgrade to v%u.%u or later"
+			 " [https://01.org/linuxgraphics/intel-linux-graphics-firmwares].\n",
+			 CSR_VERSION_MAJOR(csr->version),
+			 CSR_VERSION_MINOR(csr->version),
+			 SKL_REQUIRED_FW_MAJOR,
+			 SKL_REQUIRED_FW_MINOR);
+		goto out;
+	}
+
 	readcount += sizeof(struct intel_css_header);
 
 	/* Extract Package Header information*/
@@ -405,17 +419,20 @@ static void finish_csr_load(const struct firmware *fw, void *context)
 	intel_csr_load_program(dev);
 	fw_loaded = true;
 
-	DRM_INFO("Finished loading %s (v%u.%u)\n",
-		 dev_priv->csr.fw_path,
-		 CSR_VERSION_MAJOR(csr->version),
-		 CSR_VERSION_MINOR(csr->version));
-
 out:
-	if (fw_loaded)
+	if (fw_loaded) {
 		intel_runtime_pm_put(dev_priv);
-	else
+
+		DRM_INFO("Finished loading %s (v%u.%u)\n",
+			 dev_priv->csr.fw_path,
+			 CSR_VERSION_MAJOR(csr->version),
+			 CSR_VERSION_MINOR(csr->version));
+	} else {
 		intel_csr_load_status_set(dev_priv, FW_FAILED);
 
+		i915_firmware_load_error_print(csr->fw_path, 0);
+	}
+
 	release_firmware(fw);
 }
 
-- 
2.5.0

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Re: [PATCH 2/7] drm/i915/skl: Refuse to load outdated dmc firmware

[Imre Deak]

On ti, 2015-10-27 at 14:47 +0200, Mika Kuoppala wrote:
> There is known issue on GT interrupt delivery with DC6 and
> firmwares <1.21. There is a suspicion that this causes
> spurious gpu hangs on driver init and with some workloads,
> as upgrading the firmware to 1.21 makes these problems
> disappear.
> 
> As of now the current version included in distribution
> firmware packages is very like to be 1.19. Play it safe and
> refuse to load a firmware version that may affect gpu
> side stability.
> 
> With < 1.23 there is a palette and dmc ram corruption issue
> so blacklist anything below that.
> 
> v2: Refuse to load fw instead of notifying the user
> v3: Rebase on header version changes
> v4: Refuse to load anything less than 1.23
> v5: Give enough information for user for finding correct fw (Chris)
> v6: better url and formatting (Chris)
> v7: move error log for each fail path (Mika)
>     bail out earlier in load path (Imre)
> 
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Dave Gordon <david.s.gordon@intel.com>
> Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> References: https://01.org/linuxgraphics/downloads/skldmcver121
> References: https://01.org/linuxgraphics/downloads/skylake-dmc-1.23
> Testcase: igt/gem_exec_nop
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_csr.c | 37 +++++++++++++++++++++++++++----------
>  1 file changed, 27 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> index e620e85..701c685 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -47,6 +47,9 @@
>  MODULE_FIRMWARE(I915_CSR_SKL);
>  MODULE_FIRMWARE(I915_CSR_BXT);
>  
> +#define SKL_REQUIRED_FW_MAJOR	1
> +#define SKL_REQUIRED_FW_MINOR	23
> +
>  /*
>  * SKL CSR registers for DC5 and DC6
>  */
> @@ -303,10 +306,8 @@ static void finish_csr_load(const struct firmware *fw, void *context)
>  	uint32_t *dmc_payload;
>  	bool fw_loaded = false;
>  
> -	if (!fw) {
> -		i915_firmware_load_error_print(csr->fw_path, 0);
> +	if (!fw)
>  		goto out;
> -	}
>  
>  	if ((stepping == -ENODATA) || (substepping == -ENODATA)) {
>  		DRM_ERROR("Unknown stepping info, firmware loading failed\n");
> @@ -324,6 +325,19 @@ static void finish_csr_load(const struct firmware *fw, void *context)
>  
>  	csr->version = css_header->version;
>  
> +	if (IS_SKYLAKE(dev) &&
> +	    (CSR_VERSION_MAJOR(csr->version) < SKL_REQUIRED_FW_MAJOR ||
> +	     CSR_VERSION_MINOR(csr->version) < SKL_REQUIRED_FW_MINOR)) {

This would also reject 2.22 too for example, isn't that a problem?
If so, after fixing that:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> +		DRM_INFO("Refusing to load old Skylake DMC firmware v%u.%u,"
> +			 " please upgrade to v%u.%u or later"
> +			 " [https://01.org/linuxgraphics/intel-linux-graphics-firmwares].\n",
> +			 CSR_VERSION_MAJOR(csr->version),
> +			 CSR_VERSION_MINOR(csr->version),
> +			 SKL_REQUIRED_FW_MAJOR,
> +			 SKL_REQUIRED_FW_MINOR);
> +		goto out;
> +	}
> +
>  	readcount += sizeof(struct intel_css_header);
>  
>  	/* Extract Package Header information*/
> @@ -405,17 +419,20 @@ static void finish_csr_load(const struct firmware *fw, void *context)
>  	intel_csr_load_program(dev);
>  	fw_loaded = true;
>  
> -	DRM_INFO("Finished loading %s (v%u.%u)\n",
> -		 dev_priv->csr.fw_path,
> -		 CSR_VERSION_MAJOR(csr->version),
> -		 CSR_VERSION_MINOR(csr->version));
> -
>  out:
> -	if (fw_loaded)
> +	if (fw_loaded) {
>  		intel_runtime_pm_put(dev_priv);
> -	else
> +
> +		DRM_INFO("Finished loading %s (v%u.%u)\n",
> +			 dev_priv->csr.fw_path,
> +			 CSR_VERSION_MAJOR(csr->version),
> +			 CSR_VERSION_MINOR(csr->version));
> +	} else {
>  		intel_csr_load_status_set(dev_priv, FW_FAILED);
>  
> +		i915_firmware_load_error_print(csr->fw_path, 0);
> +	}
> +
>  	release_firmware(fw);
>  }
>  


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[PATCH 2/7] drm/i915/skl: Refuse to load outdated dmc firmware

[Mika Kuoppala]

There is known issue on GT interrupt delivery with DC6 and
firmwares <1.21. There is a suspicion that this causes
spurious gpu hangs on driver init and with some workloads,
as upgrading the firmware to 1.21 makes these problems
disappear.

As of now the current version included in distribution
firmware packages is very like to be 1.19. Play it safe and
refuse to load a firmware version that may affect gpu
side stability.

With < 1.23 there is a palette and dmc ram corruption issue
so blacklist anything below that.

v2: Refuse to load fw instead of notifying the user
v3: Rebase on header version changes
v4: Refuse to load anything less than 1.23
v5: Give enough information for user for finding correct fw (Chris)
v6: better url and formatting (Chris)
v7: move error log for each fail path (Mika)
    bail out earlier in load path (Imre)
v8: Fix the version check (Imre)

Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Dave Gordon <david.s.gordon@intel.com>
Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
References: https://01.org/linuxgraphics/downloads/skldmcver121
References: https://01.org/linuxgraphics/downloads/skylake-dmc-1.23
Testcase: igt/gem_exec_nop
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_csr.c | 34 ++++++++++++++++++++++++----------
 1 file changed, 24 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index e620e85..25b6ba7 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -47,6 +47,8 @@
 MODULE_FIRMWARE(I915_CSR_SKL);
 MODULE_FIRMWARE(I915_CSR_BXT);
 
+#define SKL_CSR_VERSION_REQUIRED	CSR_VERSION(1, 23)
+
 /*
 * SKL CSR registers for DC5 and DC6
 */
@@ -303,10 +305,8 @@ static void finish_csr_load(const struct firmware *fw, void *context)
 	uint32_t *dmc_payload;
 	bool fw_loaded = false;
 
-	if (!fw) {
-		i915_firmware_load_error_print(csr->fw_path, 0);
+	if (!fw)
 		goto out;
-	}
 
 	if ((stepping == -ENODATA) || (substepping == -ENODATA)) {
 		DRM_ERROR("Unknown stepping info, firmware loading failed\n");
@@ -324,6 +324,17 @@ static void finish_csr_load(const struct firmware *fw, void *context)
 
 	csr->version = css_header->version;
 
+	if (IS_SKYLAKE(dev) && csr->version < SKL_CSR_VERSION_REQUIRED) {
+		DRM_INFO("Refusing to load old Skylake DMC firmware v%u.%u,"
+			 " please upgrade to v%u.%u or later"
+			 " [https://01.org/linuxgraphics/intel-linux-graphics-firmwares].\n",
+			 CSR_VERSION_MAJOR(csr->version),
+			 CSR_VERSION_MINOR(csr->version),
+			 CSR_VERSION_MAJOR(SKL_CSR_VERSION_REQUIRED),
+			 CSR_VERSION_MINOR(SKL_CSR_VERSION_REQUIRED));
+		goto out;
+	}
+
 	readcount += sizeof(struct intel_css_header);
 
 	/* Extract Package Header information*/
@@ -405,17 +416,20 @@ static void finish_csr_load(const struct firmware *fw, void *context)
 	intel_csr_load_program(dev);
 	fw_loaded = true;
 
-	DRM_INFO("Finished loading %s (v%u.%u)\n",
-		 dev_priv->csr.fw_path,
-		 CSR_VERSION_MAJOR(csr->version),
-		 CSR_VERSION_MINOR(csr->version));
-
 out:
-	if (fw_loaded)
+	if (fw_loaded) {
 		intel_runtime_pm_put(dev_priv);
-	else
+
+		DRM_INFO("Finished loading %s (v%u.%u)\n",
+			 dev_priv->csr.fw_path,
+			 CSR_VERSION_MAJOR(csr->version),
+			 CSR_VERSION_MINOR(csr->version));
+	} else {
 		intel_csr_load_status_set(dev_priv, FW_FAILED);
 
+		i915_firmware_load_error_print(csr->fw_path, 0);
+	}
+
 	release_firmware(fw);
 }
 
-- 
2.5.0

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Re: [PATCH 2/7] drm/i915/skl: Refuse to load outdated dmc firmware

[Daniel Stone]

Hi Mika,

On 30 October 2015 at 15:52, Mika Kuoppala
<mika.kuoppala@linux.intel.com> wrote:
> There is known issue on GT interrupt delivery with DC6 and
> firmwares <1.21. There is a suspicion that this causes
> spurious gpu hangs on driver init and with some workloads,
> as upgrading the firmware to 1.21 makes these problems
> disappear.
>
> As of now the current version included in distribution
> firmware packages is very like to be 1.19. Play it safe and
> refuse to load a firmware version that may affect gpu
> side stability.
>
> With < 1.23 there is a palette and dmc ram corruption issue
> so blacklist anything below that.

Unfortunately 1.23 is only available from 01.org, and doesn't appear
to have been submitted to linux-firmware. Rodrigo, is this going to be
submitted soon, or?

Cheers,
Daniel
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Re: [PATCH 2/7] drm/i915/skl: Refuse to load outdated dmc firmware

[Vivi, Rodrigo]

On Tue, 2015-11-03 at 21:49 +0000, Daniel Stone wrote:
> Hi Mika,
> 
> On 30 October 2015 at 15:52, Mika Kuoppala
> <mika.kuoppala@linux.intel.com> wrote:
> > There is known issue on GT interrupt delivery with DC6 and
> > firmwares <1.21. There is a suspicion that this causes
> > spurious gpu hangs on driver init and with some workloads,
> > as upgrading the firmware to 1.21 makes these problems
> > disappear.
> > 
> > As of now the current version included in distribution
> > firmware packages is very like to be 1.19. Play it safe and
> > refuse to load a firmware version that may affect gpu
> > side stability.
> > 
> > With < 1.23 there is a palette and dmc ram corruption issue
> > so blacklist anything below that.
> 
> Unfortunately 1.23 is only available from 01.org, and doesn't appear
> to have been submitted to linux-firmware. Rodrigo, is this going to 
> be
> submitted soon, or?

I submit along with the release at 01.org.
It just got pulled and merged there.


> Cheers,
> Daniel

Thanks,
Rodrigo.
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Re: [PATCH 2/7] drm/i915/skl: Refuse to load outdated dmc firmware

[Daniel Stone]

Hi Rodrigo,

On 3 November 2015 at 23:23, Vivi, Rodrigo <rodrigo.vivi@intel.com> wrote:
> On Tue, 2015-11-03 at 21:49 +0000, Daniel Stone wrote:
>> On 30 October 2015 at 15:52, Mika Kuoppala
>> <mika.kuoppala@linux.intel.com> wrote:
>> > With < 1.23 there is a palette and dmc ram corruption issue
>> > so blacklist anything below that.
>>
>> Unfortunately 1.23 is only available from 01.org, and doesn't appear
>> to have been submitted to linux-firmware. Rodrigo, is this going to
>> be
>> submitted soon, or?
>
> I submit along with the release at 01.org.
> It just got pulled and merged there.

Yes, you're right - the reason I couldn't find the submission anywhere
is because linux-firmware@ is just an alias rather than an actual
archived list! So yes, it was actually submitted, and got merged last
night as well. Sorry about that.

Cheers,
Daniel
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[PATCH 3/7] drm/i915/skl: Print the DMC firmware status in debugfs

[Mika Kuoppala]

From: Damien Lespiau <damien.lespiau@intel.com>

Create a new debufs file for it, we'll have a few more things to add
there.

v2: Fix checkpatch warning about static const array
v3: use named initializers (Ville)
v4: strip out csr_state as it will be removed in future (Ville, Imre)

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 89ba549..2f53cb1 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2783,6 +2783,32 @@ static int i915_power_domain_info(struct seq_file *m, void *unused)
 	return 0;
 }
 
+static int i915_dmc_info(struct seq_file *m, void *unused)
+{
+	struct drm_info_node *node = m->private;
+	struct drm_device *dev = node->minor->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_csr *csr;
+
+	if (!HAS_CSR(dev)) {
+		seq_puts(m, "not supported\n");
+		return 0;
+	}
+
+	csr = &dev_priv->csr;
+
+	seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
+	seq_printf(m, "path: %s\n", csr->fw_path);
+
+	if (!csr->dmc_payload)
+		return 0;
+
+	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
+		   CSR_VERSION_MINOR(csr->version));
+
+	return 0;
+}
+
 static void intel_seq_print_mode(struct seq_file *m, int tabs,
 				 struct drm_display_mode *mode)
 {
@@ -5242,6 +5268,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
 	{"i915_energy_uJ", i915_energy_uJ, 0},
 	{"i915_runtime_pm_status", i915_runtime_pm_status, 0},
 	{"i915_power_domain_info", i915_power_domain_info, 0},
+	{"i915_dmc_info", i915_dmc_info, 0},
 	{"i915_display_info", i915_display_info, 0},
 	{"i915_semaphore_status", i915_semaphore_status, 0},
 	{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
-- 
2.5.0

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Re: [PATCH 3/7] drm/i915/skl: Print the DMC firmware status in debugfs

[Imre Deak]

On ti, 2015-10-27 at 14:47 +0200, Mika Kuoppala wrote:
> From: Damien Lespiau <damien.lespiau@intel.com>
> 
> Create a new debufs file for it, we'll have a few more things to add
> there.
> 
> v2: Fix checkpatch warning about static const array
> v3: use named initializers (Ville)
> v4: strip out csr_state as it will be removed in future (Ville, Imre)
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1)
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 89ba549..2f53cb1 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2783,6 +2783,32 @@ static int i915_power_domain_info(struct seq_file *m, void *unused)
>  	return 0;
>  }
>  
> +static int i915_dmc_info(struct seq_file *m, void *unused)
> +{
> +	struct drm_info_node *node = m->private;
> +	struct drm_device *dev = node->minor->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_csr *csr;
> +
> +	if (!HAS_CSR(dev)) {
> +		seq_puts(m, "not supported\n");
> +		return 0;
> +	}
> +
> +	csr = &dev_priv->csr;
> +
> +	seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
> +	seq_printf(m, "path: %s\n", csr->fw_path);
> +
> +	if (!csr->dmc_payload)
> +		return 0;
> +
> +	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
> +		   CSR_VERSION_MINOR(csr->version));
> +
> +	return 0;
> +}
> +
>  static void intel_seq_print_mode(struct seq_file *m, int tabs,
>  				 struct drm_display_mode *mode)
>  {
> @@ -5242,6 +5268,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
>  	{"i915_energy_uJ", i915_energy_uJ, 0},
>  	{"i915_runtime_pm_status", i915_runtime_pm_status, 0},
>  	{"i915_power_domain_info", i915_power_domain_info, 0},
> +	{"i915_dmc_info", i915_dmc_info, 0},
>  	{"i915_display_info", i915_display_info, 0},
>  	{"i915_semaphore_status", i915_semaphore_status, 0},
>  	{"i915_shared_dplls_info", i915_shared_dplls_info, 0},


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[PATCH 4/7] drm/i915/skl: Expose DC5/DC6 entry counts

[Mika Kuoppala]

From: Damien Lespiau <damien.lespiau@intel.com>

The CSR firmware expose two counters, handy to check if we are indeed
entering DC5/DC6.

v2: Rebase

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> (v1)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 7 +++++++
 drivers/gpu/drm/i915/i915_reg.h     | 4 ++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 2f53cb1..d8e9bc8 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2806,6 +2806,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
 		   CSR_VERSION_MINOR(csr->version));
 
+	if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
+		seq_printf(m, "DC3 -> DC5 count: %d\n",
+			   I915_READ(SKL_CSR_DC3_DC5_COUNT));
+		seq_printf(m, "DC5 -> DC6 count: %d\n",
+			   I915_READ(SKL_CSR_DC5_DC6_COUNT));
+	}
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8942532..bf9bddd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5696,6 +5696,10 @@ enum skl_disp_power_wells {
 #define GAMMA_MODE_MODE_12BIT	(2 << 0)
 #define GAMMA_MODE_MODE_SPLIT	(3 << 0)
 
+/* DMC/CSR */
+#define SKL_CSR_DC3_DC5_COUNT	0x80030
+#define SKL_CSR_DC5_DC6_COUNT	0x8002C
+
 /* interrupts */
 #define DE_MASTER_IRQ_CONTROL   (1 << 31)
 #define DE_SPRITEB_FLIP_DONE    (1 << 29)
-- 
2.5.0

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Re: [PATCH 4/7] drm/i915/skl: Expose DC5/DC6 entry counts

[Imre Deak]

On ti, 2015-10-27 at 14:47 +0200, Mika Kuoppala wrote:
> From: Damien Lespiau <damien.lespiau@intel.com>
> 
> The CSR firmware expose two counters, handy to check if we are indeed
> entering DC5/DC6.
> 
> v2: Rebase
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> (v1)
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 7 +++++++
>  drivers/gpu/drm/i915/i915_reg.h     | 4 ++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 2f53cb1..d8e9bc8 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2806,6 +2806,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>  	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
>  		   CSR_VERSION_MINOR(csr->version));
>  
> +	if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
> +		seq_printf(m, "DC3 -> DC5 count: %d\n",
> +			   I915_READ(SKL_CSR_DC3_DC5_COUNT));
> +		seq_printf(m, "DC5 -> DC6 count: %d\n",
> +			   I915_READ(SKL_CSR_DC5_DC6_COUNT));
> +	}
> +

These registers return all 0xFF without an RPM ref.

>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8942532..bf9bddd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5696,6 +5696,10 @@ enum skl_disp_power_wells {
>  #define GAMMA_MODE_MODE_12BIT	(2 << 0)
>  #define GAMMA_MODE_MODE_SPLIT	(3 << 0)
>  
> +/* DMC/CSR */
> +#define SKL_CSR_DC3_DC5_COUNT	0x80030
> +#define SKL_CSR_DC5_DC6_COUNT	0x8002C
> +
>  /* interrupts */
>  #define DE_MASTER_IRQ_CONTROL   (1 << 31)
>  #define DE_SPRITEB_FLIP_DONE    (1 << 29)


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[PATCH 4/7] drm/i915/skl: Expose DC5/DC6 entry counts

[Mika Kuoppala]

From: Damien Lespiau <damien.lespiau@intel.com>

The CSR firmware expose two counters, handy to check if we are indeed
entering DC5/DC6.

v2: Rebase
v3: Take RPM ref before reading (Imre)

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> (v1)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 11 +++++++++++
 drivers/gpu/drm/i915/i915_reg.h     |  4 ++++
 2 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 4ed2797..c30580b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2810,6 +2810,17 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
 		   CSR_VERSION_MINOR(csr->version));
 
+	intel_runtime_pm_get(dev_priv);
+
+	if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
+		seq_printf(m, "DC3 -> DC5 count: %d\n",
+			   I915_READ(SKL_CSR_DC3_DC5_COUNT));
+		seq_printf(m, "DC5 -> DC6 count: %d\n",
+			   I915_READ(SKL_CSR_DC5_DC6_COUNT));
+	}
+
+	intel_runtime_pm_put(dev_priv);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8942532..bf9bddd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5696,6 +5696,10 @@ enum skl_disp_power_wells {
 #define GAMMA_MODE_MODE_12BIT	(2 << 0)
 #define GAMMA_MODE_MODE_SPLIT	(3 << 0)
 
+/* DMC/CSR */
+#define SKL_CSR_DC3_DC5_COUNT	0x80030
+#define SKL_CSR_DC5_DC6_COUNT	0x8002C
+
 /* interrupts */
 #define DE_MASTER_IRQ_CONTROL   (1 << 31)
 #define DE_SPRITEB_FLIP_DONE    (1 << 29)
-- 
2.5.0

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[PATCH 5/7] drm/i915/bxt: Expose DC5 entry count

[Mika Kuoppala]

For bxt CSR firmware exposes a count of dc5 entries. Expose
it through debugs

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 3 +++
 drivers/gpu/drm/i915/i915_reg.h     | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d8e9bc8..7a61599 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2811,6 +2811,9 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 			   I915_READ(SKL_CSR_DC3_DC5_COUNT));
 		seq_printf(m, "DC5 -> DC6 count: %d\n",
 			   I915_READ(SKL_CSR_DC5_DC6_COUNT));
+	} else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
+		seq_printf(m, "DC3 -> DC5 count: %d\n",
+			   I915_READ(BXT_CSR_DC3_DC5_COUNT));
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf9bddd..c563ead 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5699,6 +5699,7 @@ enum skl_disp_power_wells {
 /* DMC/CSR */
 #define SKL_CSR_DC3_DC5_COUNT	0x80030
 #define SKL_CSR_DC5_DC6_COUNT	0x8002C
+#define BXT_CSR_DC3_DC5_COUNT	0x80038
 
 /* interrupts */
 #define DE_MASTER_IRQ_CONTROL   (1 << 31)
-- 
2.5.0

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Re: [PATCH 5/7] drm/i915/bxt: Expose DC5 entry count

[Imre Deak]

On ti, 2015-10-27 at 14:47 +0200, Mika Kuoppala wrote:
> For bxt CSR firmware exposes a count of dc5 entries. Expose
> it through debugs
> 
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 3 +++
>  drivers/gpu/drm/i915/i915_reg.h     | 1 +
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index d8e9bc8..7a61599 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2811,6 +2811,9 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>  			   I915_READ(SKL_CSR_DC3_DC5_COUNT));
>  		seq_printf(m, "DC5 -> DC6 count: %d\n",
>  			   I915_READ(SKL_CSR_DC5_DC6_COUNT));
> +	} else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
> +		seq_printf(m, "DC3 -> DC5 count: %d\n",
> +			   I915_READ(BXT_CSR_DC3_DC5_COUNT));
>  	}
>  
>  	return 0;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bf9bddd..c563ead 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5699,6 +5699,7 @@ enum skl_disp_power_wells {
>  /* DMC/CSR */
>  #define SKL_CSR_DC3_DC5_COUNT	0x80030
>  #define SKL_CSR_DC5_DC6_COUNT	0x8002C
> +#define BXT_CSR_DC3_DC5_COUNT	0x80038
>  
>  /* interrupts */
>  #define DE_MASTER_IRQ_CONTROL   (1 << 31)


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[PATCH 6/7] drm/i915: Add csr programming registers to dmc debugfs entry

[Mika Kuoppala]

We check these to determine firmware loading status. Include
them to help to debug causes of firmware loading fails.

v2: Move all CSR specific registers to i915_reg.h (Ville)
v3: Rebase

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  7 ++++++-
 drivers/gpu/drm/i915/i915_reg.h     | 10 ++++++++++
 drivers/gpu/drm/i915/intel_csr.c    | 13 -------------
 3 files changed, 16 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 7a61599..44b8c326 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2801,7 +2801,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 	seq_printf(m, "path: %s\n", csr->fw_path);
 
 	if (!csr->dmc_payload)
-		return 0;
+		goto out;
 
 	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
 		   CSR_VERSION_MINOR(csr->version));
@@ -2816,6 +2816,11 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 			   I915_READ(BXT_CSR_DC3_DC5_COUNT));
 	}
 
+out:
+	seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
+	seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
+	seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c563ead..72bbed2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5697,6 +5697,16 @@ enum skl_disp_power_wells {
 #define GAMMA_MODE_MODE_SPLIT	(3 << 0)
 
 /* DMC/CSR */
+#define CSR_PROGRAM(i)		(0x80000 + (i) * 4)
+#define CSR_SSP_BASE_ADDR_GEN9	0x00002FC0
+#define CSR_HTP_ADDR_SKL	0x00500034
+#define CSR_SSP_BASE		0x8F074
+#define CSR_HTP_SKL		0x8F004
+#define CSR_LAST_WRITE		0x8F034
+#define CSR_LAST_WRITE_VALUE	0xc003b400
+/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
+#define CSR_MMIO_START_RANGE	0x80000
+#define CSR_MMIO_END_RANGE	0x8FFFF
 #define SKL_CSR_DC3_DC5_COUNT	0x80030
 #define SKL_CSR_DC5_DC6_COUNT	0x8002C
 #define BXT_CSR_DC3_DC5_COUNT	0x80038
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 701c685..bd305da 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -50,21 +50,8 @@ MODULE_FIRMWARE(I915_CSR_BXT);
 #define SKL_REQUIRED_FW_MAJOR	1
 #define SKL_REQUIRED_FW_MINOR	23
 
-/*
-* SKL CSR registers for DC5 and DC6
-*/
-#define CSR_PROGRAM(i)			(0x80000 + (i) * 4)
-#define CSR_SSP_BASE_ADDR_GEN9		0x00002FC0
-#define CSR_HTP_ADDR_SKL		0x00500034
-#define CSR_SSP_BASE			0x8F074
-#define CSR_HTP_SKL			0x8F004
-#define CSR_LAST_WRITE			0x8F034
-#define CSR_LAST_WRITE_VALUE		0xc003b400
-/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
 #define CSR_MAX_FW_SIZE			0x2FFF
 #define CSR_DEFAULT_FW_OFFSET		0xFFFFFFFF
-#define CSR_MMIO_START_RANGE	0x80000
-#define CSR_MMIO_END_RANGE		0x8FFFF
 
 struct intel_css_header {
 	/* 0x09 for DMC */
-- 
2.5.0

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Re: [PATCH 6/7] drm/i915: Add csr programming registers to dmc debugfs entry

[Imre Deak]

On ti, 2015-10-27 at 14:47 +0200, Mika Kuoppala wrote:
> We check these to determine firmware loading status. Include
> them to help to debug causes of firmware loading fails.
> 
> v2: Move all CSR specific registers to i915_reg.h (Ville)
> v3: Rebase
> 
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c |  7 ++++++-
>  drivers/gpu/drm/i915/i915_reg.h     | 10 ++++++++++
>  drivers/gpu/drm/i915/intel_csr.c    | 13 -------------
>  3 files changed, 16 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 7a61599..44b8c326 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2801,7 +2801,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>  	seq_printf(m, "path: %s\n", csr->fw_path);
>  
>  	if (!csr->dmc_payload)
> -		return 0;
> +		goto out;
>  
>  	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
>  		   CSR_VERSION_MINOR(csr->version));
> @@ -2816,6 +2816,11 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>  			   I915_READ(BXT_CSR_DC3_DC5_COUNT));
>  	}
>  
> +out:
> +	seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
> +	seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
> +	seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c563ead..72bbed2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5697,6 +5697,16 @@ enum skl_disp_power_wells {
>  #define GAMMA_MODE_MODE_SPLIT	(3 << 0)
>  
>  /* DMC/CSR */
> +#define CSR_PROGRAM(i)		(0x80000 + (i) * 4)
> +#define CSR_SSP_BASE_ADDR_GEN9	0x00002FC0
> +#define CSR_HTP_ADDR_SKL	0x00500034
> +#define CSR_SSP_BASE		0x8F074
> +#define CSR_HTP_SKL		0x8F004
> +#define CSR_LAST_WRITE		0x8F034
> +#define CSR_LAST_WRITE_VALUE	0xc003b400
> +/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
> +#define CSR_MMIO_START_RANGE	0x80000
> +#define CSR_MMIO_END_RANGE	0x8FFFF
>  #define SKL_CSR_DC3_DC5_COUNT	0x80030
>  #define SKL_CSR_DC5_DC6_COUNT	0x8002C
>  #define BXT_CSR_DC3_DC5_COUNT	0x80038
> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> index 701c685..bd305da 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -50,21 +50,8 @@ MODULE_FIRMWARE(I915_CSR_BXT);
>  #define SKL_REQUIRED_FW_MAJOR	1
>  #define SKL_REQUIRED_FW_MINOR	23
>  
> -/*
> -* SKL CSR registers for DC5 and DC6
> -*/
> -#define CSR_PROGRAM(i)			(0x80000 + (i) * 4)
> -#define CSR_SSP_BASE_ADDR_GEN9		0x00002FC0
> -#define CSR_HTP_ADDR_SKL		0x00500034
> -#define CSR_SSP_BASE			0x8F074
> -#define CSR_HTP_SKL			0x8F004
> -#define CSR_LAST_WRITE			0x8F034
> -#define CSR_LAST_WRITE_VALUE		0xc003b400
> -/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
>  #define CSR_MAX_FW_SIZE			0x2FFF
>  #define CSR_DEFAULT_FW_OFFSET		0xFFFFFFFF
> -#define CSR_MMIO_START_RANGE	0x80000
> -#define CSR_MMIO_END_RANGE		0x8FFFF
>  
>  struct intel_css_header {
>  	/* 0x09 for DMC */


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[PATCH 6/7] drm/i915: Add csr programming registers to dmc debugfs entry

[Mika Kuoppala]

We check these to determine firmware loading status. Include
them to help to debug causes of firmware loading fails.

v2: Move all CSR specific registers to i915_reg.h (Ville)
v3: Rebase
v4: Rebase (RPM ref)

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 11 ++++++++---
 drivers/gpu/drm/i915/i915_reg.h     | 10 ++++++++++
 drivers/gpu/drm/i915/intel_csr.c    | 13 -------------
 3 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 2c33770..f6468be 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2801,17 +2801,17 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 
 	csr = &dev_priv->csr;
 
+	intel_runtime_pm_get(dev_priv);
+
 	seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
 	seq_printf(m, "path: %s\n", csr->fw_path);
 
 	if (!csr->dmc_payload)
-		return 0;
+		goto out;
 
 	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
 		   CSR_VERSION_MINOR(csr->version));
 
-	intel_runtime_pm_get(dev_priv);
-
 	if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
 		seq_printf(m, "DC3 -> DC5 count: %d\n",
 			   I915_READ(SKL_CSR_DC3_DC5_COUNT));
@@ -2822,6 +2822,11 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 			   I915_READ(BXT_CSR_DC3_DC5_COUNT));
 	}
 
+out:
+	seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
+	seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
+	seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
+
 	intel_runtime_pm_put(dev_priv);
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c563ead..72bbed2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5697,6 +5697,16 @@ enum skl_disp_power_wells {
 #define GAMMA_MODE_MODE_SPLIT	(3 << 0)
 
 /* DMC/CSR */
+#define CSR_PROGRAM(i)		(0x80000 + (i) * 4)
+#define CSR_SSP_BASE_ADDR_GEN9	0x00002FC0
+#define CSR_HTP_ADDR_SKL	0x00500034
+#define CSR_SSP_BASE		0x8F074
+#define CSR_HTP_SKL		0x8F004
+#define CSR_LAST_WRITE		0x8F034
+#define CSR_LAST_WRITE_VALUE	0xc003b400
+/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
+#define CSR_MMIO_START_RANGE	0x80000
+#define CSR_MMIO_END_RANGE	0x8FFFF
 #define SKL_CSR_DC3_DC5_COUNT	0x80030
 #define SKL_CSR_DC5_DC6_COUNT	0x8002C
 #define BXT_CSR_DC3_DC5_COUNT	0x80038
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 25b6ba7..7dc5390 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -49,21 +49,8 @@ MODULE_FIRMWARE(I915_CSR_BXT);
 
 #define SKL_CSR_VERSION_REQUIRED	CSR_VERSION(1, 23)
 
-/*
-* SKL CSR registers for DC5 and DC6
-*/
-#define CSR_PROGRAM(i)			(0x80000 + (i) * 4)
-#define CSR_SSP_BASE_ADDR_GEN9		0x00002FC0
-#define CSR_HTP_ADDR_SKL		0x00500034
-#define CSR_SSP_BASE			0x8F074
-#define CSR_HTP_SKL			0x8F004
-#define CSR_LAST_WRITE			0x8F034
-#define CSR_LAST_WRITE_VALUE		0xc003b400
-/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
 #define CSR_MAX_FW_SIZE			0x2FFF
 #define CSR_DEFAULT_FW_OFFSET		0xFFFFFFFF
-#define CSR_MMIO_START_RANGE	0x80000
-#define CSR_MMIO_END_RANGE		0x8FFFF
 
 struct intel_css_header {
 	/* 0x09 for DMC */
-- 
2.5.0

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[PATCH 7/7] drm/i915: Add dmc firmware load state and version to error state

[Mika Kuoppala]

We have had one case where buggy csr/dmc firmware version influenced
gt side and caused a hang. Add dmc firmware loading state and
version to error state.

v2: - Rebased on top of Damien's patches
    - included fw load state
v3: include dmc info only if platform supports it (Chris)
v4: move *csr to branch scope (Chris)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 793f2de..aaf4a1f 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -366,6 +366,16 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 	err_printf(m, "Suspend count: %u\n", error->suspend_count);
 	err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
 	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
+
+	if (HAS_CSR(dev)) {
+		struct intel_csr *csr = &dev_priv->csr;
+
+		err_printf(m, "DMC load state: %d\n", csr->state);
+		err_printf(m, "DMC fw version: %d.%d\n",
+			   CSR_VERSION_MAJOR(csr->version),
+			   CSR_VERSION_MINOR(csr->version));
+	}
+
 	err_printf(m, "EIR: 0x%08x\n", error->eir);
 	err_printf(m, "IER: 0x%08x\n", error->ier);
 	if (INTEL_INFO(dev)->gen >= 8) {
-- 
2.5.0

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[PATCH 7/7] drm/i915: Add dmc firmware load state and version to error state

[Mika Kuoppala]

We have had one case where buggy csr/dmc firmware version influenced
gt side and caused a hang. Add dmc firmware loading state and
version to error state.

v2: - Rebased on top of Damien's patches
    - included fw load state
v3: include dmc info only if platform supports it (Chris)
v4: move *csr to branch scope (Chris)
v5: remove dependency to csr_state

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v4)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 793f2de..27b6ac9 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -366,6 +366,17 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 	err_printf(m, "Suspend count: %u\n", error->suspend_count);
 	err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
 	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
+
+	if (HAS_CSR(dev)) {
+		struct intel_csr *csr = &dev_priv->csr;
+
+		err_printf(m, "DMC loaded: %s\n",
+			   yesno(csr->dmc_payload != NULL));
+		err_printf(m, "DMC fw version: %d.%d\n",
+			   CSR_VERSION_MAJOR(csr->version),
+			   CSR_VERSION_MINOR(csr->version));
+	}
+
 	err_printf(m, "EIR: 0x%08x\n", error->eir);
 	err_printf(m, "IER: 0x%08x\n", error->ier);
 	if (INTEL_INFO(dev)->gen >= 8) {
-- 
2.5.0

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Re: [PATCH 1/7] drm/i915/skl: Store and print the DMC firmware version we load

[Imre Deak]

On ti, 2015-10-27 at 14:46 +0200, Mika Kuoppala wrote:
> From: Damien Lespiau <damien.lespiau@intel.com>
> 
> That can be handy later on to tell which DMC firmware version the user
> has, by just looking at the dmesg.
> 
> v2: use DRM_DEBUG_DRIVER (Chris)
> v3: use DRM_INFO (Marc Herbert)
> 
> Cc: Marc Herbert <marc.herbert@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1)
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h  | 5 +++++
>  drivers/gpu/drm/i915/intel_csr.c | 9 ++++++++-
>  2 files changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b408ebf..0bee438 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -734,6 +734,10 @@ struct intel_uncore {
>  #define for_each_fw_domain(domain__, dev_priv__, i__) \
>  	for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
>  
> +#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
> +#define CSR_VERSION_MAJOR(version)	((version) >> 16)
> +#define CSR_VERSION_MINOR(version)	((version) & 0xffff)
> +
>  enum csr_state {
>  	FW_UNINITIALIZED = 0,
>  	FW_LOADED,
> @@ -744,6 +748,7 @@ struct intel_csr {
>  	const char *fw_path;
>  	uint32_t *dmc_payload;
>  	uint32_t dmc_fw_size;
> +	uint32_t version;
>  	uint32_t mmio_count;
>  	uint32_t mmioaddr[8];
>  	uint32_t mmiodata[8];
> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> index 9e530a7..e620e85 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -321,6 +321,9 @@ static void finish_csr_load(const struct firmware *fw, void *context)
>  			(css_header->header_len * 4));
>  		goto out;
>  	}
> +
> +	csr->version = css_header->version;
> +
>  	readcount += sizeof(struct intel_css_header);
>  
>  	/* Extract Package Header information*/
> @@ -402,7 +405,11 @@ static void finish_csr_load(const struct firmware *fw, void *context)
>  	intel_csr_load_program(dev);
>  	fw_loaded = true;
>  
> -	DRM_DEBUG_KMS("Finished loading %s\n", dev_priv->csr.fw_path);
> +	DRM_INFO("Finished loading %s (v%u.%u)\n",
> +		 dev_priv->csr.fw_path,
> +		 CSR_VERSION_MAJOR(csr->version),
> +		 CSR_VERSION_MINOR(csr->version));
> +
>  out:
>  	if (fw_loaded)
>  		intel_runtime_pm_put(dev_priv);


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Re: [PATCH 1/7] drm/i915/skl: Store and print the DMC firmware version we load

[Daniel Stone]

Hi,

On 27 October 2015 at 12:46, Mika Kuoppala
<mika.kuoppala@linux.intel.com> wrote:
> From: Damien Lespiau <damien.lespiau@intel.com>
>
> That can be handy later on to tell which DMC firmware version the user
> has, by just looking at the dmesg.
>
> v2: use DRM_DEBUG_DRIVER (Chris)
> v3: use DRM_INFO (Marc Herbert)

For the series (all 7):
Tested-by: Daniel Stone <daniels@collabora.com> # SKL

Cheers,
Daniel
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Re: [PATCH 1/7] drm/i915/skl: Store and print the DMC firmware version we load

[Ville Syrjälä]

On Wed, Nov 04, 2015 at 05:18:28PM +0000, Daniel Stone wrote:
> Hi,
> 
> On 27 October 2015 at 12:46, Mika Kuoppala
> <mika.kuoppala@linux.intel.com> wrote:
> > From: Damien Lespiau <damien.lespiau@intel.com>
> >
> > That can be handy later on to tell which DMC firmware version the user
> > has, by just looking at the dmesg.
> >
> > v2: use DRM_DEBUG_DRIVER (Chris)
> > v3: use DRM_INFO (Marc Herbert)
> 
> For the series (all 7):
> Tested-by: Daniel Stone <daniels@collabora.com> # SKL

Entire series merged. Thanks for patches, reviews and testing.

There was no trace on the mailing list where Imre's r-b on patch 4/7
came from, but I confirmed with Imre that it was given on irc.

-- 
Ville Syrjälä
Intel OTC
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[PATCH 1/7] drm/i915/skl: Print the DMC firmware status in debugfs

[Mika Kuoppala]

From: Damien Lespiau <damien.lespiau@intel.com>

Create a new debufs file for it, we'll have a few more things to add
there.

v2: Fix checkpatch warning about static const array

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a3b22bd..ceae425 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2777,6 +2777,27 @@ static int i915_power_domain_info(struct seq_file *m, void *unused)
 	return 0;
 }
 
+static int i915_dmc_info(struct seq_file *m, void *unused)
+{
+	struct drm_info_node *node = m->private;
+	struct drm_device *dev = node->minor->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	enum csr_state csr_state;
+	static const char * const csr_state_str[] = {
+		"unknown", "loaded", "error"
+	};
+
+	if (!HAS_CSR(dev)) {
+		seq_puts(m, "not supported\n");
+		return 0;
+	}
+
+	csr_state = intel_csr_load_status_get(dev_priv);
+	seq_printf(m, "status: %s\n", csr_state_str[csr_state]);
+
+	return 0;
+}
+
 static void intel_seq_print_mode(struct seq_file *m, int tabs,
 				 struct drm_display_mode *mode)
 {
@@ -5236,6 +5257,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
 	{"i915_energy_uJ", i915_energy_uJ, 0},
 	{"i915_runtime_pm_status", i915_runtime_pm_status, 0},
 	{"i915_power_domain_info", i915_power_domain_info, 0},
+	{"i915_dmc_info", i915_dmc_info, 0},
 	{"i915_display_info", i915_display_info, 0},
 	{"i915_semaphore_status", i915_semaphore_status, 0},
 	{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
-- 
2.1.4

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[PATCH 5/7] drm/i915/bxt: Expose DC5 entry count

[Mika Kuoppala]

For bxt CSR firmware exposes a count of dc5 entries. Expose
it through debugs

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 3 +++
 drivers/gpu/drm/i915/i915_reg.h     | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d9440cc..5d606f0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2807,6 +2807,9 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 			   I915_READ(SKL_CSR_DC3_DC5_COUNT));
 		seq_printf(m, "DC5 -> DC6 count: %d\n",
 			   I915_READ(SKL_CSR_DC5_DC6_COUNT));
+	} else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
+		seq_printf(m, "DC3 -> DC5 count: %d\n",
+			   I915_READ(BXT_CSR_DC3_DC5_COUNT));
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb03892..05f4a18 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5699,6 +5699,7 @@ enum skl_disp_power_wells {
 /* DMC/CSR */
 #define SKL_CSR_DC3_DC5_COUNT	0x80030
 #define SKL_CSR_DC5_DC6_COUNT	0x8002C
+#define BXT_CSR_DC3_DC5_COUNT	0x80038
 
 /* interrupts */
 #define DE_MASTER_IRQ_CONTROL   (1 << 31)
-- 
2.1.4

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