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From: Shobhit Kumar <shobhit.kumar@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Shobhit Kumar <shobhit.kumar@intel.com>
Subject: [PATCH] drm/i915/skl: While sanitizing cdclock check the SWF18 as well
Date: Mon,  2 Nov 2015 17:25:08 +0530	[thread overview]
Message-ID: <1446465308-3639-2-git-send-email-shobhit.kumar@intel.com> (raw)
In-Reply-To: <1446465308-3639-1-git-send-email-shobhit.kumar@intel.com>

SWF18 is set if the display has been intialized by the pre-os. It
also gives what configuration is enabled on which pipe. The DPLL and
CDCLK verification checks can fail as the pre-os does initialize the
DPLL for Audio codec initialization. So fisrt check if SWF18 is set and
then follow through with other DPLL and CDCLK verification.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      | 3 +++
 drivers/gpu/drm/i915/intel_display.c | 8 ++++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9ee9481..bd476ff 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5006,6 +5006,9 @@ enum skl_disp_power_wells {
 #define SWF1(i)	(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
 #define SWF3(i)	(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
 
+/* VBIOS flag for display initialized status */
+#define GEN6_SWF18  (dev_priv->info.display_mmio_offset + 0x4F060)
+
 /* Pipe B */
 #define _PIPEBDSL		(dev_priv->info.display_mmio_offset + 0x71000)
 #define _PIPEBCONF		(dev_priv->info.display_mmio_offset + 0x71008)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 103cacb..0ecb35c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5761,6 +5761,14 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 	uint32_t cdctl = I915_READ(CDCLK_CTL);
 	int freq = dev_priv->skl_boot_cdclk;
 
+	/*
+	 * check if the pre-os intialized the display
+	 * There is SWF18 scratchpad register defined which is set by the
+	 * pre-os which can be used by the OS drivers to check the status
+	 */
+	if ((I915_READ(GEN6_SWF18) & 0x00FFFF) == 0)
+		goto sanitize;
+
 	/* Is PLL enabled and locked ? */
 	if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
 		goto sanitize;
-- 
2.4.3

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  reply	other threads:[~2015-11-02 11:55 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-11-02 11:55 [PATCH] CDCLOCK Sanitization continued for SKL Shobhit Kumar
2015-11-02 11:55 ` Shobhit Kumar [this message]
2015-11-02 13:10   ` [PATCH] drm/i915/skl: While sanitizing cdclock check the SWF18 as well Jani Nikula
2015-11-02 13:19     ` Kumar, Shobhit
2015-11-02 16:37       ` Thulasimani, Sivakumar
2015-11-02 17:47         ` Kumar, Shobhit
2015-11-02 18:18           ` Thulasimani, Sivakumar
2015-11-03  2:59             ` Kumar, Shobhit
2015-11-05  7:43             ` [v2] " Shobhit Kumar
2015-11-05  9:35               ` [v3] " Shobhit Kumar
2015-11-05  9:38                 ` Thulasimani, Sivakumar
2015-11-05 11:23                 ` Ville Syrjälä
2015-11-05 12:35                   ` [v4] " Shobhit Kumar
2015-11-05 13:04                     ` Jani Nikula
2015-11-04  3:47   ` [PATCH] " Kumar, Shobhit
2015-11-03  3:12 ` [PATCH] CDCLOCK Sanitization continued for SKL Kumar, Shobhit

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