Re: [PATCH 1/3] drm/i915: Also delay first activation for SKL+

["Vivi, Rodrigo" <rodrigo.vivi@intel.com>]

On Thu, 2015-11-19 at 08:44 +0000, Daniel Stone wrote:
> Hi Rodrigo,
> 
> On 19 November 2015 at 00:39, Rodrigo Vivi <rodrigo.vivi@intel.com> 
> wrote:
> > @@ -441,15 +438,14 @@ void intel_psr_enable(struct intel_dp 
> > *intel_dp)
> >         /*
> >          * FIXME: Activation should happen immediately since this 
> > function
> >          * is just called after pipe is fully trained and enabled.
> > -        * However on every platform we face issues when first 
> > activation
> > +        * However on some platforms we face issues when first 
> > activation
> >          * follows a modeset so quickly.
> >          *     - On VLV/CHV we get bank screen on first activation
> >          *     - On HSW/BDW we get a recoverable frozen screen 
> > until next
> >          *       exit-activate sequence.
> >          */
> > -       if (INTEL_INFO(dev)->gen < 9)
> > -               schedule_delayed_work(&dev_priv->psr.work,
> > -                                     msecs_to_jiffies(intel_dp
> > ->panel_power_cycle_delay * 5));
> > +       schedule_delayed_work(&dev_priv->psr.work,
> > +                             msecs_to_jiffies(intel_dp
> > ->panel_power_cycle_delay * 5));
> 
> The comment change here seems to be the exact opposite of the code
> change:

Indeed, this is why I'll keep the fixme on the comment.

>  aren't we now seeing these issues on every platform? If not,
> it would be good to elaborate on the issues seen in SKL/BSW.

So far no known issue on SKL/KBL. (BSW is CHV)
But since we have no idea why these issues are happening and separated
handling was causing confusion I preferred to handle all with the
protection.

Regarding the issue itself, the Hardware needs to communicate with the
Sink using AUX channels. I believe there is just kind of strange
conflict going on there because the failures are exactly when we are
also using aux channels for our modeset/link-trainings.
This is also why I used panel_power_cycle_delay * 5 there because it is
the same value we use to force VDD on while we are doing the aux
transactions.

Please let me know if you have further questions, concerns or
suggestions here.

Thanks
> 
> Cheers,
> Daniel
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