From: Imre Deak <imre.deak@intel.com>
To: marius.c.vlad@intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH i-g-t] tests/pm_rpm tests for set_caching and set_tiling ioctl(s)
Date: Wed, 25 Nov 2015 22:08:21 +0200 [thread overview]
Message-ID: <1448482101.32235.136.camel@intel.com> (raw)
In-Reply-To: <1448471779-24328-2-git-send-email-marius.c.vlad@intel.com>
On ke, 2015-11-25 at 19:16 +0200, marius.c.vlad@intel.com wrote:
> From: Marius Vlad <marius.c.vlad@intel.com>
>
> Signed-off-by: Marius Vlad <marius.c.vlad@intel.com>
> ---
> tests/pm_rpm.c | 120 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 120 insertions(+)
>
> diff --git a/tests/pm_rpm.c b/tests/pm_rpm.c
> index c4fb19c..157cf29 100644
> --- a/tests/pm_rpm.c
> +++ b/tests/pm_rpm.c
> @@ -1729,6 +1729,120 @@ static void planes_subtest(bool universal, bool dpms)
> }
> }
>
> +static void pm_test_tiling(void)
> +{
> + uint32_t *handles;
> + uint8_t **gem_bufs;
> +
> + int max_gem_objs = 0;
> + uint8_t off_bit = 20;
> + uint32_t gtt_obj_max_size = (16 * 1024 * 1024);
> +
> + uint32_t i, j, tiling_modes[3] = {
> + I915_TILING_NONE,
> + I915_TILING_X,
> + I915_TILING_Y,
> + };
> + uint32_t ti, sw;
> +
> + /* default value */
> + uint32_t stride = 1024;
> +
> + /* calculate how many objects we can map */
> + for (j = 1 << off_bit; j <= gtt_obj_max_size; j <<= 1, max_gem_objs++)
> + ;
With these sizes we may end up with all objects properly aligned,
that's why I suggested smaller objects. Based on I830_FENCE_START_MASK
we could allocate for example starting from 16kB to 256kB.
> +
> + gem_bufs = calloc(max_gem_objs, sizeof(uint8_t *));
> + handles = malloc(sizeof(uint32_t) * max_gem_objs);
Nitpick: sizeof(*ptr) is safer and you could've used calloc in both
cases.
> +
> + /* map to gtt and store some random data */
> + for (i = 0, j = 1 << off_bit; j <= gtt_obj_max_size; j <<= 1, i++) {
> + handles[i] = gem_create(drm_fd, j);
> + gem_bufs[i] = gem_mmap__gtt(drm_fd, handles[i], j, PROT_WRITE);
> + memset(gem_bufs[i], 0x65, j);
> + }
> +
> + /* try to set different tiling for each handle */
> + for (i = 0; i < ARRAY_SIZE(tiling_modes); i++) {
> + disable_all_screens_and_wait(&ms_data);
> +
> + for (j = 0; j < max_gem_objs; j++) {
> + gem_set_tiling(drm_fd, handles[j], tiling_modes[i], stride);
> +
> + gem_get_tiling(drm_fd, handles[j], &ti, &sw);
> + igt_assert(tiling_modes[i] == ti);
> + }
> +
> + enable_one_screen_and_wait(&ms_data);
Ok, but after the second iteration all objects could be properly
aligned, so it's better to close/realloc/memset the objects in each
iteration.
> + }
> +
> + for (i = 0, j = 1 << off_bit; j <= gtt_obj_max_size; j <<= 1, i++) {
> + igt_assert(munmap(gem_bufs[i], j) == 0);
> + gem_close(drm_fd, handles[i]);
> + }
> +
> + free(gem_bufs);
> + free(handles);
> +}
> +
> +static void pm_test_caching(void)
> +{
> + uint32_t *handles;
> + uint8_t **gem_bufs;
> + int8_t has_caching_display = -1;
> +
> + uint32_t i, j, got_caching;
> + uint32_t gtt_obj_max_size = (16 * 1024 * 1024);
> + uint32_t cache_levels[3] = {
> + I915_CACHING_NONE,
> + I915_CACHING_CACHED, /* LLC caching */
> + I915_CACHING_DISPLAY, /* eDRAM caching */
> + };
> +
> + int max_gem_objs = 0;
> + uint8_t off_bit = 20;
> +
> + for (j = 1 << off_bit; j <= gtt_obj_max_size; j <<= 1, max_gem_objs++)
> + ;
No need to bother about alignment here, so we can just use a single
16kB object for example.
> +
> + gem_bufs = calloc(max_gem_objs, sizeof(uint8_t *));
> + handles = malloc(sizeof(uint32_t) * max_gem_objs);
> +
> + for (i = 0, j = 1 << off_bit; j <= gtt_obj_max_size; j <<= 1, i++) {
> + handles[i] = gem_create(drm_fd, j);
> + gem_bufs[i] = gem_mmap__gtt(drm_fd, handles[i], j, PROT_WRITE);
> + memset(gem_bufs[i], 0x65, j);
> + }
> +
> + /* figure out if we have cache display available on the platform */
> + gem_set_caching(drm_fd, handles[0], I915_CACHING_DISPLAY);
> + if (gem_get_caching(drm_fd, handles[0]))
No need to hardcode I915_CACHING_NONE here. Also I liked the original
version to check this everywhere better, by accepting both
CACHING_DISPLAY and CACHING_NONE as a result.
> + has_caching_display++;
> +
> + for (i = 0; i < ARRAY_SIZE(cache_levels) + has_caching_display; i++) {
> + disable_all_screens_and_wait(&ms_data);
> +
> + for (j = 0; j < max_gem_objs; j++) {
> + gem_set_caching(drm_fd, handles[j], cache_levels[i]);
> +
> + igt_debug("Verying cache for handle %u, level %u\n", j, i);
> + got_caching = gem_get_caching(drm_fd, handles[j]);
> +
> + igt_assert(got_caching == cache_levels[i]);
> + }
> +
> + enable_one_screen_and_wait(&ms_data);
The object can be unbound after the IOCTL so you need to do a memset at
the begin of each iteration.
> + }
> +
> + for (i = 0, j = 1 << off_bit; j <= gtt_obj_max_size; j <<= 1, i++) {
> + igt_assert(munmap(gem_bufs[i], j) == 0);
> + gem_close(drm_fd, handles[i]);
> + }
> +
> + free(handles);
> + free(gem_bufs);
> +}
> +
> static void fences_subtest(bool dpms)
> {
> int i;
> @@ -1927,6 +2041,12 @@ int main(int argc, char *argv[])
> igt_subtest("gem-execbuf-stress-extra-wait")
> gem_execbuf_stress_subtest(rounds, WAIT_STATUS | WAIT_EXTRA);
>
> + /* power-wake reference tests */
> + igt_subtest("pm-tiling")
> + pm_test_tiling();
> + igt_subtest("pm-caching")
> + pm_test_caching();
> +
> igt_fixture
> teardown_environment();
>
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next prev parent reply other threads:[~2015-11-25 20:08 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-24 17:42 [PATCH i-g-t] tests/pm_rpm tests for set_caching and set_tiling ioctl(s) marius.c.vlad
2015-11-24 22:57 ` Imre Deak
2015-11-25 17:16 ` [PATCH i-g-t v2] " marius.c.vlad
2015-11-25 17:16 ` [PATCH i-g-t] " marius.c.vlad
2015-11-25 20:08 ` Imre Deak [this message]
2015-11-26 10:55 ` Marius Vlad
2015-11-26 11:57 ` Imre Deak
2015-11-26 16:32 ` Marius Vlad
2015-11-26 18:23 ` Imre Deak
2015-11-27 18:08 ` [PATCH i-g-t v4] tests/pm_rpm tests for set_caching and set_tiling Marius Vlad
2015-11-27 18:08 ` [PATCH i-g-t] tests/pm_rpm tests for set_caching and set_tiling ioctl(s) Marius Vlad
2015-11-27 19:51 ` Imre Deak
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