[RFC 18/22] drm/i915/slpc: Add dfps task info to i915_slpc_info

[tom.orourke@intel.com]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 12 ++++++++++++
 drivers/gpu/drm/i915/intel_slpc.c   | 31 +++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h   |  1 +
 3 files changed, 44 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 3fc8f83..b705aff 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1137,6 +1137,12 @@ static int i915_slpc_info(struct seq_file *m, void *unused)
 	enum slpc_power_source power_source;
 
 	if (HAS_SLPC(dev)) {
+		ret = intel_slpc_query_task_state(dev);
+		if (ret) {
+			seq_printf(m, "query task state failed: %d\n", ret);
+			ret = 0;
+		}
+
 		obj = dev_priv->guc.slpc.shared_data_obj;
 		if (obj) {
 			page = i915_gem_object_get_page(obj, 0);
@@ -1259,6 +1265,12 @@ static int i915_slpc_info(struct seq_file *m, void *unused)
 			   data->platform_info.package_rapl_limit_low);
 		seq_printf(m, "task state data: 0x%8x\n",
 			   data->task_state_data);
+		seq_printf(m, "task state dfps: task active %d ",
+			   (data->task_state_data & 1));
+		seq_printf(m, "stall possible %d game mode %d target fps %d\n",
+			   (data->task_state_data & 2),
+			   (data->task_state_data & 4),
+			   (data->task_state_data >> 3) & 0xFF);
 
 		seq_puts(m, "override parameter bitfield\n");
 		for (i=0; i < SLPC_OVERRIDE_BITFIELD_SIZE; i++)
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index c15ab19..36aedb9 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -95,6 +95,30 @@ static int host2guc_slpc_display_mode_change(struct drm_i915_private *dev_priv)
 	return ret;
 }
 
+static int host2guc_slpc_query_task_state(struct drm_i915_private *dev_priv)
+{
+	struct drm_i915_gem_object *obj = dev_priv->guc.slpc.shared_data_obj;
+        u32 data[4];
+	int ret;
+	u64 shared_data_gtt_offset = i915_gem_obj_ggtt_offset(obj);
+
+        data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+        data[1] = SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2);
+	data[2] = lower_32_bits(shared_data_gtt_offset);
+	data[3] = upper_32_bits(shared_data_gtt_offset);
+
+	WARN_ON(0 != data[3]);
+
+        ret = host2guc_action(&dev_priv->guc, data, 4);
+
+	if (0 == ret) {
+		ret = I915_READ(SOFT_SCRATCH(1));
+		ret &= 0xFF;
+	}
+
+	return ret;
+}
+
 static u8 slpc_get_platform_sku(struct drm_i915_gem_object *obj)
 {
 	struct drm_device *dev = obj->base.dev;
@@ -339,3 +363,10 @@ int intel_slpc_update_display_rr_info(struct drm_device *dev, u32 refresh_rate)
 
 	return 0;
 }
+
+int intel_slpc_query_task_state(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	return host2guc_slpc_query_task_state(dev_priv);
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index e7ff4a0..32d7dcc 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -181,4 +181,5 @@ int intel_slpc_reset(struct drm_device *dev);
 int intel_slpc_update_display_mode_info(struct drm_device *dev);
 int intel_slpc_update_display_rr_info(struct drm_device *dev, u32 refresh_rate);
 
+int intel_slpc_query_task_state(struct drm_device *dev);
 #endif
-- 
1.9.1

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