From: Arun Siluvery <arun.siluvery@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v2 5/8] drm/i915/bxt: Add GEN8_L3SQCREG4 to HW whitelist
Date: Thu, 21 Jan 2016 14:00:44 +0000 [thread overview]
Message-ID: <1453384847-16361-6-git-send-email-arun.siluvery@linux.intel.com> (raw)
In-Reply-To: <1453384847-16361-1-git-send-email-arun.siluvery@linux.intel.com>
Required for WaDisableLSQCROPERFforOCL:bxt
According to WA database these are only applicable for BXT:A0 but since
A0 and A1 shares the same GT these are extended for A1 as well.
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 72e89b6..1decaf1 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1134,10 +1134,15 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
/* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
/* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
/* WaDisableObjectLevelPreemtionForInstanceId:bxt */
+ /* WaDisableLSQCROPERFforOCL:bxt */
if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
ret = wa_ring_whitelist_reg(ring, GEN9_CS_DEBUG_MODE1);
if (ret)
return ret;
+
+ ret = wa_ring_whitelist_reg(ring, GEN8_L3SQCREG4);
+ if (ret)
+ return ret;
}
return 0;
--
1.9.1
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next prev parent reply other threads:[~2016-01-21 14:01 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-21 14:00 [PATCH v2 0/8] Gen9 HW whitelist and Preemption WA patches Arun Siluvery
2016-01-21 14:00 ` [PATCH v2 1/8] drm/i915/gen9: Add framework to whitelist specific GPU registers Arun Siluvery
2016-01-21 14:00 ` [PATCH v2 2/8] drm/i915/gen9: Add GEN8_CS_CHICKEN1 to HW whitelist Arun Siluvery
2016-01-21 14:00 ` [PATCH v2 3/8] drm/i915/gen9: Add HDC_CHICKEN1 " Arun Siluvery
2016-01-21 14:00 ` [PATCH v2 4/8] drm/i915/bxt: Add GEN9_CS_DEBUG_MODE1 " Arun Siluvery
2016-01-21 14:40 ` Nick Hoath
2016-01-21 14:00 ` Arun Siluvery [this message]
2016-01-21 14:00 ` [PATCH v2 6/8] drm/i915/skl: Add GEN8_L3SQCREG4 " Arun Siluvery
2016-01-21 14:00 ` [PATCH v2 7/8] drm/i915/skl: Enable Per context Preemption granularity control Arun Siluvery
2016-01-21 14:41 ` Nick Hoath
2016-01-21 14:00 ` [PATCH v2 8/8] drm/i915/gen9: Add WaOCLCoherentLineFlush Arun Siluvery
2016-01-21 14:42 ` Nick Hoath
2016-01-21 14:25 ` ✗ Fi.CI.BAT: warning for Gen9 HW whitelist and Preemption WA patches (rev2) Patchwork
2016-01-21 14:36 ` Arun Siluvery
2016-01-21 15:17 ` [PATCH v2 0/8] Gen9 HW whitelist and Preemption WA patches Chris Wilson
2016-01-21 16:07 ` Arun Siluvery
2016-01-21 16:56 ` Chris Wilson
2016-01-21 17:35 ` Arun Siluvery
2016-01-25 18:01 ` Daniel Vetter
2016-01-25 18:23 ` Arun Siluvery
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