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From: Arun Siluvery <arun.siluvery@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v3 2/8] drm/i915/gen9: Add GEN8_CS_CHICKEN1 to HW whitelist
Date: Thu, 21 Jan 2016 21:43:48 +0000	[thread overview]
Message-ID: <1453412634-29238-3-git-send-email-arun.siluvery@linux.intel.com> (raw)
In-Reply-To: <1453412634-29238-1-git-send-email-arun.siluvery@linux.intel.com>

Required for WaEnablePreemptionGranularityControlByUMD:skl,bxt

This register is added to HW whitelist to support WA required for future
enabling of pre-emptive command execution, WA implementation will be in
userspace and it cannot program this register if it is not on HW whitelist.

v2: explain purpose of WA (Chris)

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 2 ++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7938814..511732e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5998,6 +5998,8 @@ enum skl_disp_power_wells {
 #define FF_SLICE_CS_CHICKEN2			_MMIO(0x20e4)
 #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)
 
+#define GEN8_CS_CHICKEN1		_MMIO(0x2580)
+
 /* GEN7 chicken */
 #define GEN7_COMMON_SLICE_CHICKEN1		_MMIO(0x7010)
 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 56af736..47d8767 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -908,6 +908,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 	struct drm_device *dev = ring->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t tmp;
+	int ret;
 
 	/* WaEnableLbsSlaRetryTimerDecrement:skl */
 	I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
@@ -978,6 +979,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 	/* WaDisableSTUnitPowerOptimization:skl,bxt */
 	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 
+	/* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
+	ret= wa_ring_whitelist_reg(ring, GEN8_CS_CHICKEN1);
+	if (ret)
+		return ret;
+
 	return 0;
 }
 
-- 
1.9.1

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  parent reply	other threads:[~2016-01-21 21:44 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-01-21 21:43 [PATCH v3 0/8] Gen9 HW whitelist and Preemption WA patches Arun Siluvery
2016-01-21 21:43 ` [PATCH v3 1/8] drm/i915/gen9: Add framework to whitelist specific GPU registers Arun Siluvery
2016-01-21 21:43 ` Arun Siluvery [this message]
2016-01-21 21:43 ` [PATCH v3 3/8] drm/i915/gen9: Add HDC_CHICKEN1 to HW whitelist Arun Siluvery
2016-01-21 21:43 ` [PATCH v3 4/8] drm/i915/bxt: Add GEN9_CS_DEBUG_MODE1 " Arun Siluvery
2016-01-21 21:43 ` [PATCH v3 5/8] drm/i915/bxt: Add GEN8_L3SQCREG4 " Arun Siluvery
2016-01-21 21:43 ` [PATCH v3 6/8] drm/i915/skl: " Arun Siluvery
2016-01-21 21:43 ` [PATCH v3 7/8] drm/i915/skl: Enable Per context Preemption granularity control Arun Siluvery
2016-01-21 21:43 ` [PATCH v3 8/8] drm/i915/gen9: Add WaOCLCoherentLineFlush Arun Siluvery
2016-01-22  8:51 ` ✗ Fi.CI.BAT: warning for Gen9 HW whitelist and Preemption WA patches (rev3) Patchwork
2016-01-22 10:07   ` Arun Siluvery

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