From: Arun Siluvery <arun.siluvery@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v3 6/8] drm/i915/skl: Add GEN8_L3SQCREG4 to HW whitelist
Date: Thu, 21 Jan 2016 21:43:52 +0000 [thread overview]
Message-ID: <1453412634-29238-7-git-send-email-arun.siluvery@linux.intel.com> (raw)
In-Reply-To: <1453412634-29238-1-git-send-email-arun.siluvery@linux.intel.com>
Required for WaDisableLSQCROPERFforOCL:skl
This register is added to HW whitelist to support WA required for future
enabling of pre-emptive command execution, WA implementation will be in
userspace and it cannot program this register if it is not on HW whitelist.
v2: explain purpose of changes (Chris)
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1decaf1..ce64519 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1096,6 +1096,11 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
GEN7_HALF_SLICE_CHICKEN1,
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
+ /* WaDisableLSQCROPERFforOCL:skl */
+ ret = wa_ring_whitelist_reg(ring, GEN8_L3SQCREG4);
+ if (ret)
+ return ret;
+
return skl_tune_iz_hashing(ring);
}
--
1.9.1
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next prev parent reply other threads:[~2016-01-21 21:44 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-21 21:43 [PATCH v3 0/8] Gen9 HW whitelist and Preemption WA patches Arun Siluvery
2016-01-21 21:43 ` [PATCH v3 1/8] drm/i915/gen9: Add framework to whitelist specific GPU registers Arun Siluvery
2016-01-21 21:43 ` [PATCH v3 2/8] drm/i915/gen9: Add GEN8_CS_CHICKEN1 to HW whitelist Arun Siluvery
2016-01-21 21:43 ` [PATCH v3 3/8] drm/i915/gen9: Add HDC_CHICKEN1 " Arun Siluvery
2016-01-21 21:43 ` [PATCH v3 4/8] drm/i915/bxt: Add GEN9_CS_DEBUG_MODE1 " Arun Siluvery
2016-01-21 21:43 ` [PATCH v3 5/8] drm/i915/bxt: Add GEN8_L3SQCREG4 " Arun Siluvery
2016-01-21 21:43 ` Arun Siluvery [this message]
2016-01-21 21:43 ` [PATCH v3 7/8] drm/i915/skl: Enable Per context Preemption granularity control Arun Siluvery
2016-01-21 21:43 ` [PATCH v3 8/8] drm/i915/gen9: Add WaOCLCoherentLineFlush Arun Siluvery
2016-01-22 8:51 ` ✗ Fi.CI.BAT: warning for Gen9 HW whitelist and Preemption WA patches (rev3) Patchwork
2016-01-22 10:07 ` Arun Siluvery
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