From: tim.gore@intel.com
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 2/3] drm/i915/gen8: add WaIncreaseDefaultTLBEntries
Date: Mon, 25 Jan 2016 14:16:36 +0000 [thread overview]
Message-ID: <1453731397-12877-3-git-send-email-tim.gore@intel.com> (raw)
In-Reply-To: <1453731397-12877-1-git-send-email-tim.gore@intel.com>
From: Tim Gore <tim.gore@intel.com>
Add WaIncreaseDefaultTLBEntries:chv,bdw.
This workaround provides significant perfromance boost
for some OpenCL workloads by adjusting the L3_LRA_1_GPGPU
register.
This is for bdw/chv. Further patches will provide the
workaround for other sku's.
Signed-off-by: Tim Gore <tim.gore@intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +++++
drivers/gpu/drm/i915/i915_reg.h | 5 +++++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index fe960d5..be87318 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2140,6 +2140,11 @@ void gtt_write_workarounds(struct drm_device *dev)
* called on driver load and after a GPU reset, so you can place
* workarounds here even if they get overwritten by GPU reset.
*/
+ /* WaIncreaseDefaultTLBEntries:chv,bdw */
+ if (IS_BROADWELL(dev))
+ I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
+ else if (IS_CHERRYVIEW(dev))
+ I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
}
int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a98889..513e2980 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8159,4 +8159,9 @@ enum skl_disp_power_wells {
#define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */
#define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */
+/* gamt regs */
+#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
+#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
+#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */
+
#endif /* _I915_REG_H_ */
--
1.9.1
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next prev parent reply other threads:[~2016-01-25 14:16 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-25 14:16 [PATCH 0/3] drm/i915: add WaIncreaseDefaultTLBEntries tim.gore
2016-01-25 14:16 ` [PATCH 1/3] drm/i915: add function for GT related workarounds tim.gore
2016-01-25 14:39 ` Mika Kuoppala
2016-01-25 14:43 ` Gore, Tim
2016-01-25 16:17 ` Chris Wilson
2016-01-25 16:41 ` Arun Siluvery
2016-01-25 17:10 ` Chris Wilson
2016-01-25 18:04 ` Arun Siluvery
2016-01-26 9:31 ` Gore, Tim
2016-01-25 14:16 ` tim.gore [this message]
2016-01-25 14:16 ` [PATCH 3/3] drm/i915/gen9: add WaIncreaseDefaultTLBEntries tim.gore
2016-01-25 14:40 ` Mika Kuoppala
2016-01-27 15:32 ` ✓ Fi.CI.BAT: success for drm/i915: " Patchwork
2016-01-28 13:47 ` Patchwork
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