From: Zhi Wang <zhi.a.wang@intel.com>
To: intel-gfx@lists.freedesktop.org, igvt-g@lists.01.org
Cc: daniel.vetter@ffwll.ch, david.j.cowperthwaite@intel.com
Subject: [RFC 11/29] drm/i915: gvt: update PVINFO page definition in i915_vgpu.h
Date: Thu, 28 Jan 2016 18:21:33 +0800 [thread overview]
Message-ID: <1453976511-27322-12-git-send-email-zhi.a.wang@intel.com> (raw)
In-Reply-To: <1453976511-27322-1-git-send-email-zhi.a.wang@intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
drivers/gpu/drm/i915/i915_vgpu.h | 85 +++++++++++++++++++++++++++++++++-------
1 file changed, 70 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index b8a49e6..21c77a2 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -42,24 +42,47 @@
INTEL_VGT_IF_VERSION_ENCODE(VGT_VERSION_MAJOR, VGT_VERSION_MINOR)
/*
- * notifications from guest to vgpu device model
+ * The information set by the guest gfx driver, through the display_ready field
+ */
+#define VGT_DRV_DISPLAY_NOT_READY (0 << 0)
+#define VGT_DRV_DISPLAY_READY (1 << 0) /* ready for display switch */
+#define VGT_DRV_LEGACY_VGA_MODE (1 << 1) /* in the legacy VGA mode */
+
+/*
+ * guest-to-vgt notifications
*/
enum vgt_g2v_type {
- VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2,
+ VGT_G2V_DISPLAY_REFRESH,
+ VGT_G2V_SET_POINTER_SHAPE,
+ VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE,
VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY,
VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE,
VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
- VGT_G2V_EXECLIST_CONTEXT_CREATE,
- VGT_G2V_EXECLIST_CONTEXT_DESTROY,
+ VGT_G2V_EXECLIST_CONTEXT_ELEMENT_CREATE,
+ VGT_G2V_EXECLIST_CONTEXT_ELEMENT_DESTROY,
VGT_G2V_MAX,
};
+/*
+ * vgt-to-guest notifications
+ */
+enum vgt_v2g_type {
+ VGT_V2G_SET_HW_CURSOR,
+ VGT_V2G_SET_SW_CURSOR,
+ VGT_V2G_MAX,
+};
+
+enum vgt_caps_type {
+ VGT_CAPS_PREEMPTION = (1 << 0),
+};
+
struct vgt_if {
uint64_t magic; /* VGT_MAGIC */
uint16_t version_major;
uint16_t version_minor;
uint32_t vgt_id; /* ID of vGT instance */
- uint32_t rsv1[12]; /* pad to offset 0x40 */
+ uint32_t vgt_caps; /* VGT capabilties */
+ uint32_t rsv1[11]; /* pad to offset 0x40 */
/*
* Data structure to describe the balooning info of resources.
* Each VM can only have one portion of continuous area for now.
@@ -85,13 +108,44 @@ struct vgt_if {
/*
* The bottom half page is for response from Gfx driver to hypervisor.
*/
- uint32_t rsv4;
- uint32_t display_ready; /* ready for display owner switch */
+ uint16_t drv_version_major;
+ uint16_t drv_version_minor;
+ uint32_t display_ready;/* ready for display owner switch */
+ /*
+ * driver reported status/error code
+ * 0: if the avail_rs is sufficient to driver
+ * Bit 2,1,0 set indicating
+ * Insufficient low_gmadr, high_gmadr, fence resources.
+ * Other bits are reserved.
+ */
+ uint32_t rs_insufficient;
+ /*
+ * The driver is required to update the following field with minimal
+ * required resource size.
+ */
+ uint32_t min_low_gmadr;
+ uint32_t min_high_gmadr;
+ uint32_t min_fence_num;
+
+ /*
+ * notifications between guest and vgt
+ */
+ uint32_t g2v_notify;
+ uint32_t v2g_notify;
- uint32_t rsv5[4];
+ /*
+ * PPGTT PTE table info
+ */
+ uint32_t gmm_gtt_seg_base;
+ uint32_t rsv4;
+ uint32_t gmm_gtt_seg_size;
+ uint32_t rsv5;
- uint32_t g2v_notify;
- uint32_t rsv6[7];
+ /*
+ * Cursor hotspot info
+ */
+ uint32_t xhot;
+ uint32_t yhot;
struct {
uint32_t lo;
@@ -101,16 +155,17 @@ struct vgt_if {
uint32_t execlist_context_descriptor_lo;
uint32_t execlist_context_descriptor_hi;
- uint32_t rsv7[0x200 - 24]; /* pad to one page */
+ /*
+ * scratch space for debugging
+ */
+ uint32_t scratch;;
+
+ uint32_t rsv6[0x200-25]; /* pad to one page */
} __packed;
#define vgtif_reg(x) \
_MMIO((VGT_PVINFO_PAGE + (long)&((struct vgt_if *)NULL)->x))
-/* vGPU display status to be used by the host side */
-#define VGT_DRV_DISPLAY_NOT_READY 0
-#define VGT_DRV_DISPLAY_READY 1 /* ready for display switch */
-
extern void i915_check_vgpu(struct drm_device *dev);
extern int intel_vgt_balloon(struct drm_device *dev);
extern void intel_vgt_deballoon(void);
--
1.9.1
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next prev parent reply other threads:[~2016-01-28 10:24 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-28 10:21 [RFC 00/29] iGVT-g implementation in i915 Zhi Wang
2016-01-28 10:21 ` [RFC 01/29] drm/i915/gvt: Introduce the basic architecture of GVT-g Zhi Wang
2016-01-29 13:57 ` Joonas Lahtinen
2016-01-29 16:48 ` Chris Wilson
2016-02-03 6:28 ` Zhi Wang
2016-02-05 7:02 ` Zhiyuan Lv
2016-02-03 6:01 ` Zhi Wang
2016-02-03 7:01 ` Zhiyuan Lv
2016-02-04 11:25 ` Joonas Lahtinen
2016-02-16 9:54 ` Zhi Wang
2016-02-16 12:44 ` Jani Nikula
2016-02-16 14:08 ` Joonas Lahtinen
2016-01-28 10:21 ` [RFC 02/29] drm/i915: Introduce host graphics memory balloon for gvt Zhi Wang
2016-02-04 11:27 ` Joonas Lahtinen
2016-02-05 10:03 ` Zhiyuan Lv
2016-02-05 13:40 ` Joonas Lahtinen
2016-02-05 14:16 ` Zhiyuan Lv
2016-02-08 11:52 ` Joonas Lahtinen
2016-02-10 8:08 ` Daniel Vetter
2016-01-28 10:21 ` [RFC 03/29] drm/i915: Introduce GVT context creation API Zhi Wang
2016-01-28 10:21 ` [RFC 04/29] drm/i915: Ondemand populate context addressing mode bit Zhi Wang
2016-01-28 10:21 ` [RFC 05/29] drm/i915: Do not populate PPGTT root pointers for GVT context Zhi Wang
2016-01-28 10:21 ` [RFC 06/29] drm/i915: Do not initialize the engine state of " Zhi Wang
2016-01-28 10:21 ` [RFC 07/29] drm/i915: GVT context scheduling Zhi Wang
2016-01-28 10:21 ` [RFC 08/29] drm/i915: Support vGPU guest framebuffer GEM object Zhi Wang
2016-01-28 10:21 ` [RFC 09/29] drm/i915: gvt: Resource allocator Zhi Wang
2016-01-28 10:21 ` [RFC 10/29] drm/i915: gvt: Basic mmio emulation state Zhi Wang
2016-01-28 10:21 ` Zhi Wang [this message]
2016-01-28 10:21 ` [RFC 12/29] drm/i915: gvt: vGPU life cycle management Zhi Wang
2016-01-28 10:21 ` [RFC 13/29] drm/i915: gvt: trace stub Zhi Wang
2016-01-28 10:21 ` [RFC 14/29] drm/i915: gvt: vGPU interrupt emulation framework Zhi Wang
2016-01-28 10:21 ` [RFC 15/29] drm/i915: gvt: vGPU graphics memory " Zhi Wang
2016-01-28 10:21 ` [RFC 16/29] drm/i915: gvt: Generic MPT framework Zhi Wang
2016-01-28 10:21 ` [RFC 17/29] gvt: Xen hypervisor GVT-g MPT module Zhi Wang
2016-01-28 11:33 ` Joonas Lahtinen
2016-01-28 12:50 ` Zhiyuan Lv
2016-01-28 10:21 ` [RFC 18/29] drm/i915: gvt: vGPU configuration emulation Zhi Wang
2016-01-28 10:21 ` [RFC 19/29] drm/i915: gvt: vGPU OpRegion emulation Zhi Wang
2016-01-28 10:21 ` [RFC 20/29] drm/i915: gvt: vGPU framebuffer format decoder Zhi Wang
2016-01-28 10:21 ` [RFC 21/29] drm/i915: gvt: vGPU MMIO register emulation Zhi Wang
2016-01-28 10:21 ` [RFC 22/29] drm/i915: gvt: Full display virtualization Zhi Wang
2016-01-28 10:21 ` [RFC 23/29] drm/i915: gvt: Introduce GVT control interface Zhi Wang
2016-01-28 10:21 ` [RFC 24/29] drm/i915: gvt: Full execlist status emulation Zhi Wang
2016-01-28 10:21 ` [RFC 25/29] drm/i915: gvt: vGPU execlist workload submission Zhi Wang
2016-01-28 10:21 ` [RFC 26/29] drm/i915: gvt: workload scheduler Zhi Wang
2016-01-28 10:21 ` [RFC 27/29] drm/i915: gvt: vGPU schedule policy framework Zhi Wang
2016-01-28 10:21 ` [RFC 28/29] drm/i915: gvt: vGPU context switch Zhi Wang
2016-01-28 10:21 ` [RFC 29/29] drm/i915: gvt: vGPU command scanner Zhi Wang
2016-01-28 17:15 ` ✗ Fi.CI.BAT: failure for iGVT-g implementation in i915 Patchwork
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