[PATCH 1/2] drm/i915/dp: abstract training pattern selection

[PATCH 1/2] drm/i915/dp: abstract training pattern selection

[Jani Nikula]

Make it cleaner to add more checks in the function. No functional
changes.

Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Cc: drm-intel-fixes@lists.freedesktop.org # dependency on the next patch
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dp_link_training.c | 25 ++++++++++++++++++-------
 1 file changed, 18 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
index 88887938e0bf..83e667b92fda 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -215,16 +215,15 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 	}
 }
 
-static void
-intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
+/*
+ * Pick training pattern for channel equalization. Training Pattern 3 for HBR2
+ * or 1.2 devices that support it, Training Pattern 2 otherwise.
+ */
+static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
 {
-	bool channel_eq = false;
-	int tries, cr_tries;
-	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
+	u32 training_pattern = DP_TRAINING_PATTERN_2;
 
 	/*
-	 * Training Pattern 3 for HBR2 or 1.2 devices that support it.
-	 *
 	 * Intel platforms that support HBR2 also support TPS3. TPS3 support is
 	 * also mandatory for downstream devices that support HBR2.
 	 *
@@ -237,6 +236,18 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 	else if (intel_dp->link_rate == 540000)
 		DRM_ERROR("5.4 Gbps link rate without HBR2/TPS3 support\n");
 
+	return training_pattern;
+}
+
+static void
+intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
+{
+	bool channel_eq = false;
+	int tries, cr_tries;
+	u32 training_pattern;
+
+	training_pattern = intel_dp_training_pattern(intel_dp);
+
 	/* channel equalization */
 	if (!intel_dp_set_link_train(intel_dp,
 				     training_pattern |
-- 
2.1.4

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[PATCH 2/2] drm/i915/dp: reduce missing TPS3 support errors to debug logging

[Jani Nikula]

Per spec, TPS3 support is mandatory for downstream devices that support
HBR2. We've therefore logged errors on HBR2 without TPS3 since

commit 1da7d7131c35cde83f1bab8ec732b57b69bef814
Author: Jani Nikula <jani.nikula@intel.com>
Date:   Thu Sep 3 11:16:08 2015 +0300

    drm/i915: ignore link rate in TPS3 selection

However, it seems there are real world devices out there that just
aren't spec compliant, and still work at HBR2 using TPS2. So reduce the
error message to debug logging.

Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92932
Fixes: 1da7d7131c35 ("drm/i915: ignore link rate in TPS3 selection")
Cc: drm-intel-fixes@lists.freedesktop.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dp_link_training.c | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
index 83e667b92fda..0b8eefc2acc5 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -222,19 +222,27 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
 {
 	u32 training_pattern = DP_TRAINING_PATTERN_2;
+	bool source_tps3, sink_tps3;
 
 	/*
 	 * Intel platforms that support HBR2 also support TPS3. TPS3 support is
-	 * also mandatory for downstream devices that support HBR2.
+	 * also mandatory for downstream devices that support HBR2. However, not
+	 * all sinks follow the spec.
 	 *
 	 * Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is
-	 * supported but still not enabled.
+	 * supported in source but still not enabled.
 	 */
-	if (intel_dp_source_supports_hbr2(intel_dp) &&
-	    drm_dp_tps3_supported(intel_dp->dpcd))
+	source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
+	sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
+
+	if (source_tps3 && sink_tps3) {
 		training_pattern = DP_TRAINING_PATTERN_3;
-	else if (intel_dp->link_rate == 540000)
-		DRM_ERROR("5.4 Gbps link rate without HBR2/TPS3 support\n");
+	} else if (intel_dp->link_rate == 540000) {
+		if (!source_tps3)
+			DRM_DEBUG_KMS("5.4 Gbps link rate without source HBR2/TPS3 support\n");
+		if (!sink_tps3)
+			DRM_DEBUG_KMS("5.4 Gbps link rate without sink TPS3 support\n");
+	}
 
 	return training_pattern;
 }
-- 
2.1.4

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✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dp: abstract training pattern selection

[Patchwork]

== Summary ==

Series 3120v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/3120/revisions/1/mbox/

Test kms_flip:
        Subgroup basic-flip-vs-dpms:
                dmesg-warn -> PASS       (ilk-hp8440p) UNSTABLE
Test pm_rpm:
        Subgroup basic-pci-d3-state:
                dmesg-warn -> PASS       (skl-i5k-2)

bdw-nuci7        total:161  pass:152  dwarn:0   dfail:0   fail:0   skip:9  
bdw-ultra        total:164  pass:152  dwarn:0   dfail:0   fail:0   skip:12 
bsw-nuc-2        total:164  pass:136  dwarn:0   dfail:0   fail:0   skip:28 
byt-nuc          total:164  pass:141  dwarn:0   dfail:0   fail:0   skip:23 
hsw-brixbox      total:164  pass:151  dwarn:0   dfail:0   fail:0   skip:13 
hsw-gt2          total:164  pass:154  dwarn:0   dfail:0   fail:0   skip:10 
ilk-hp8440p      total:164  pass:116  dwarn:0   dfail:0   fail:0   skip:48 
ivb-t430s        total:164  pass:150  dwarn:0   dfail:0   fail:0   skip:14 
skl-i5k-2        total:164  pass:149  dwarn:1   dfail:0   fail:0   skip:14 
snb-dellxps      total:164  pass:142  dwarn:0   dfail:0   fail:0   skip:22 
snb-x220t        total:164  pass:142  dwarn:0   dfail:0   fail:1   skip:21 

Results at /archive/results/CI_IGT_test/Patchwork_1367/

57e229193395068adcb34c5266d54194e652869f drm-intel-nightly: 2016y-02m-04d-18h-38m-55s UTC integration manifest
40076067dd294abb76241fbdd4e5ba7261a3df41 drm/i915/dp: reduce missing TPS3 support errors to debug logging
173ef8cfe90938cdbd60724deead3989885275e0 drm/i915/dp: abstract training pattern selection

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Re: [PATCH 1/2] drm/i915/dp: abstract training pattern selection

[Thulasimani, Sivakumar]

Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>

On 2/5/2016 3:46 PM, Jani Nikula wrote:
> Make it cleaner to add more checks in the function. No functional
> changes.
>
> Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com>
> Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
> Cc: drm-intel-fixes@lists.freedesktop.org # dependency on the next patch
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dp_link_training.c | 25 ++++++++++++++++++-------
>   1 file changed, 18 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
> index 88887938e0bf..83e667b92fda 100644
> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> @@ -215,16 +215,15 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
>   	}
>   }
>   
> -static void
> -intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
> +/*
> + * Pick training pattern for channel equalization. Training Pattern 3 for HBR2
> + * or 1.2 devices that support it, Training Pattern 2 otherwise.
> + */
> +static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
>   {
> -	bool channel_eq = false;
> -	int tries, cr_tries;
> -	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
> +	u32 training_pattern = DP_TRAINING_PATTERN_2;
>   
>   	/*
> -	 * Training Pattern 3 for HBR2 or 1.2 devices that support it.
> -	 *
>   	 * Intel platforms that support HBR2 also support TPS3. TPS3 support is
>   	 * also mandatory for downstream devices that support HBR2.
>   	 *
> @@ -237,6 +236,18 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
>   	else if (intel_dp->link_rate == 540000)
>   		DRM_ERROR("5.4 Gbps link rate without HBR2/TPS3 support\n");
>   
> +	return training_pattern;
> +}
> +
> +static void
> +intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
> +{
> +	bool channel_eq = false;
> +	int tries, cr_tries;
> +	u32 training_pattern;
> +
> +	training_pattern = intel_dp_training_pattern(intel_dp);
> +
>   	/* channel equalization */
>   	if (!intel_dp_set_link_train(intel_dp,
>   				     training_pattern |

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Re: [PATCH 2/2] drm/i915/dp: reduce missing TPS3 support errors to debug logging

[Thulasimani, Sivakumar]

Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>

On 2/5/2016 3:46 PM, Jani Nikula wrote:
> Per spec, TPS3 support is mandatory for downstream devices that support
> HBR2. We've therefore logged errors on HBR2 without TPS3 since
>
> commit 1da7d7131c35cde83f1bab8ec732b57b69bef814
> Author: Jani Nikula <jani.nikula@intel.com>
> Date:   Thu Sep 3 11:16:08 2015 +0300
>
>      drm/i915: ignore link rate in TPS3 selection
>
> However, it seems there are real world devices out there that just
> aren't spec compliant, and still work at HBR2 using TPS2. So reduce the
> error message to debug logging.
>
> Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com>
> Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92932
> Fixes: 1da7d7131c35 ("drm/i915: ignore link rate in TPS3 selection")
> Cc: drm-intel-fixes@lists.freedesktop.org
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dp_link_training.c | 20 ++++++++++++++------
>   1 file changed, 14 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
> index 83e667b92fda..0b8eefc2acc5 100644
> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> @@ -222,19 +222,27 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
>   static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
>   {
>   	u32 training_pattern = DP_TRAINING_PATTERN_2;
> +	bool source_tps3, sink_tps3;
>   
>   	/*
>   	 * Intel platforms that support HBR2 also support TPS3. TPS3 support is
> -	 * also mandatory for downstream devices that support HBR2.
> +	 * also mandatory for downstream devices that support HBR2. However, not
> +	 * all sinks follow the spec.
>   	 *
>   	 * Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is
> -	 * supported but still not enabled.
> +	 * supported in source but still not enabled.
>   	 */
> -	if (intel_dp_source_supports_hbr2(intel_dp) &&
> -	    drm_dp_tps3_supported(intel_dp->dpcd))
> +	source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
> +	sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
> +
> +	if (source_tps3 && sink_tps3) {
>   		training_pattern = DP_TRAINING_PATTERN_3;
> -	else if (intel_dp->link_rate == 540000)
> -		DRM_ERROR("5.4 Gbps link rate without HBR2/TPS3 support\n");
> +	} else if (intel_dp->link_rate == 540000) {
> +		if (!source_tps3)
> +			DRM_DEBUG_KMS("5.4 Gbps link rate without source HBR2/TPS3 support\n");
> +		if (!sink_tps3)
> +			DRM_DEBUG_KMS("5.4 Gbps link rate without sink TPS3 support\n");
> +	}
>   
>   	return training_pattern;
>   }

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Re: [PATCH 1/2] drm/i915/dp: abstract training pattern selection

[Jani Nikula]

On Fri, 05 Feb 2016, "Thulasimani, Sivakumar" <sivakumar.thulasimani@intel.com> wrote:
> Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>

Both pushed to drm-intel-next-queued, thanks for the review.

BR,
Jani.



>
> On 2/5/2016 3:46 PM, Jani Nikula wrote:
>> Make it cleaner to add more checks in the function. No functional
>> changes.
>>
>> Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com>
>> Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
>> Cc: drm-intel-fixes@lists.freedesktop.org # dependency on the next patch
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_dp_link_training.c | 25 ++++++++++++++++++-------
>>   1 file changed, 18 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
>> index 88887938e0bf..83e667b92fda 100644
>> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
>> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
>> @@ -215,16 +215,15 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
>>   	}
>>   }
>>   
>> -static void
>> -intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
>> +/*
>> + * Pick training pattern for channel equalization. Training Pattern 3 for HBR2
>> + * or 1.2 devices that support it, Training Pattern 2 otherwise.
>> + */
>> +static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
>>   {
>> -	bool channel_eq = false;
>> -	int tries, cr_tries;
>> -	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
>> +	u32 training_pattern = DP_TRAINING_PATTERN_2;
>>   
>>   	/*
>> -	 * Training Pattern 3 for HBR2 or 1.2 devices that support it.
>> -	 *
>>   	 * Intel platforms that support HBR2 also support TPS3. TPS3 support is
>>   	 * also mandatory for downstream devices that support HBR2.
>>   	 *
>> @@ -237,6 +236,18 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
>>   	else if (intel_dp->link_rate == 540000)
>>   		DRM_ERROR("5.4 Gbps link rate without HBR2/TPS3 support\n");
>>   
>> +	return training_pattern;
>> +}
>> +
>> +static void
>> +intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
>> +{
>> +	bool channel_eq = false;
>> +	int tries, cr_tries;
>> +	u32 training_pattern;
>> +
>> +	training_pattern = intel_dp_training_pattern(intel_dp);
>> +
>>   	/* channel equalization */
>>   	if (!intel_dp_set_link_train(intel_dp,
>>   				     training_pattern |
>
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-- 
Jani Nikula, Intel Open Source Technology Center
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