From: Zhi Wang <zhi.a.wang@intel.com>
To: intel-gfx@lists.freedesktop.org, igvt-g@lists.01.org
Cc: daniel.vetter@ffwll.ch, david.j.cowperthwaite@intel.com,
zhiyuan.lv@intel.com
Subject: [RFCv2 13/14] drm/i915: Support context single submission when GVT is active
Date: Thu, 18 Feb 2016 19:42:20 +0800 [thread overview]
Message-ID: <1455795741-3487-14-git-send-email-zhi.a.wang@intel.com> (raw)
In-Reply-To: <1455795741-3487-1-git-send-email-zhi.a.wang@intel.com>
This patch introduces a new request picking logic to support the single-
submission context. As GVT context may comes from different guests, which
requires different configuration of render registers configuration. It
can't be combined in a dual ELSP submission combo.
We make this function as a context feature in context creation service.
Only GVT-g will create this kinds of GEM context currently, which only
allows to be single submitted.
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_lrc.c | 42 +++++++++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_lrc.h | 1 +
3 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1f94df2..0850b35 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -890,6 +890,7 @@ struct intel_context {
bool need_status_change_notification;
struct atomic_notifier_head notifier_head;
} engine[I915_NUM_RINGS];
+ bool single_submission;
bool root_pointer_dirty;
struct list_head link;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 1c0366a..2a6d6fe 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -479,6 +479,40 @@ static void execlists_i915_pick_requests(struct intel_engine_cs *ring,
}
}
+static void execlists_gvt_pick_requests(struct intel_engine_cs *ring,
+ struct drm_i915_gem_request **req0,
+ struct drm_i915_gem_request **req1)
+{
+ struct drm_i915_gem_request *cursor, *tmp;
+
+ *req0 = *req1 = NULL;
+
+ /* Try to read in pairs */
+ list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
+ execlist_link) {
+ if (!*req0) {
+ *req0 = cursor;
+ /* single submission */
+ if ((*req0)->ctx->single_submission)
+ break;
+ } else if ((*req0)->ctx == cursor->ctx) {
+ /*
+ * Same ctx: ignore first request, as second request
+ * will update tail past first request's workload
+ */
+ cursor->elsp_submitted = (*req0)->elsp_submitted;
+ list_move_tail(&(*req0)->execlist_link,
+ &ring->execlist_retired_req_list);
+ *req0 = cursor;
+ } else {
+ /* single submission */
+ if (!cursor->ctx->single_submission)
+ *req1 = cursor;
+ break;
+ }
+ }
+}
+
static void execlists_context_unqueue(struct intel_engine_cs *ring)
{
struct drm_i915_gem_request *req0, *req1;
@@ -494,7 +528,10 @@ static void execlists_context_unqueue(struct intel_engine_cs *ring)
if (list_empty(&ring->execlist_queue))
return;
- execlists_i915_pick_requests(ring, &req0, &req1);
+ if (!intel_gvt_active(ring->dev))
+ execlists_i915_pick_requests(ring, &req0, &req1);
+ else
+ execlists_gvt_pick_requests(ring, &req0, &req1);
if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {
/*
@@ -2629,6 +2666,9 @@ int __intel_lr_context_deferred_alloc(struct intel_context *ctx,
&ctx->engine[ring->id].notifier_head);
}
+ if (params->ctx_needs_single_submission)
+ ctx->single_submission = true;
+
return 0;
error_ringbuf:
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 15791d4..4873dd8 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -107,6 +107,7 @@ struct intel_lr_context_alloc_params {
u32 ringbuffer_size;
bool ctx_needs_init;
bool ctx_needs_status_change_notification;
+ bool ctx_needs_single_submission;
};
void intel_lr_context_free(struct intel_context *ctx);
--
1.9.1
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next prev parent reply other threads:[~2016-02-18 11:45 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-18 11:42 [RFCv2 PATCH 00/14] gvt: Hacking i915 for GVT context requirement Zhi Wang
2016-02-18 11:42 ` [RFCv2 01/14] drm/i915: factor out i915_pvinfo.h Zhi Wang
2016-02-22 13:23 ` Joonas Lahtinen
2016-02-23 2:40 ` Zhi Wang
2016-02-18 11:42 ` [RFCv2 02/14] drm/i915/gvt: Introduce the basic architecture of GVT-g Zhi Wang
2016-02-23 12:42 ` Joonas Lahtinen
2016-02-24 7:45 ` Tian, Kevin
2016-02-25 11:24 ` Joonas Lahtinen
2016-02-26 5:58 ` Zhi Wang
2016-02-23 12:53 ` Joonas Lahtinen
2016-02-24 7:50 ` Tian, Kevin
2016-02-24 8:08 ` Tian, Kevin
2016-02-26 5:38 ` Zhi Wang
2016-02-18 11:42 ` [RFCv2 03/14] drm/i915: Introduce host graphics memory/fence partition for GVT-g Zhi Wang
2016-02-23 13:16 ` Joonas Lahtinen
2016-02-23 13:23 ` Zhi Wang
2016-02-24 7:42 ` Tian, Kevin
2016-02-25 13:13 ` Joonas Lahtinen
2016-02-26 5:21 ` Zhi Wang
2016-02-26 13:54 ` Joonas Lahtinen
2016-02-23 13:26 ` Joonas Lahtinen
2016-02-24 8:22 ` Tian, Kevin
2016-02-26 5:29 ` Zhi Wang
2016-02-18 11:42 ` [RFCv2 04/14] drm/i915: factor out alloc_context_idr() and __i915_gem_create_context() Zhi Wang
2016-02-24 8:27 ` Tian, Kevin
2016-02-18 11:42 ` [RFCv2 05/14] drm/i915: factor out __create_legacy_hw_context() Zhi Wang
2016-02-18 11:42 ` [RFCv2 06/14] drm/i915: let __i915_gem_context_create() takes context creation params Zhi Wang
2016-02-24 8:35 ` Tian, Kevin
2016-02-18 11:42 ` [RFCv2 07/14] drm/i915: factor out __intel_lr_context_deferred_alloc() Zhi Wang
2016-02-24 8:37 ` Tian, Kevin
2016-02-18 11:42 ` [RFCv2 08/14] drm/i915: Support per-PPGTT address space mode Zhi Wang
2016-02-24 8:47 ` Tian, Kevin
2016-02-18 11:42 ` [RFCv2 09/14] drm/i915: generate address mode bit from PPGTT instance Zhi Wang
2016-02-18 11:42 ` [RFCv2 10/14] drm/i915: update PDPs by condition when submit the LRC context Zhi Wang
2016-02-24 8:49 ` Tian, Kevin
2016-02-25 15:02 ` Wang, Zhi A
2016-02-26 13:49 ` Joonas Lahtinen
2016-02-18 11:42 ` [RFCv2 11/14] drm/i915: Introduce execlist context status change notification Zhi Wang
2016-02-18 11:42 ` [RFCv2 12/14] drm/i915: factor out execlists_i915_pick_requests() Zhi Wang
2016-02-18 11:42 ` Zhi Wang [this message]
2016-02-24 8:52 ` [RFCv2 13/14] drm/i915: Support context single submission when GVT is active Tian, Kevin
2016-02-18 11:42 ` [RFCv2 14/14] drm/i915: Introduce GVT context creation API Zhi Wang
2016-02-18 12:02 ` ✗ Fi.CI.BAT: failure for gvt: Hacking i915 for GVT context requirement Patchwork
2016-02-24 8:55 ` [RFCv2 PATCH 00/14] " Tian, Kevin
2016-02-24 9:18 ` Wang, Zhi A
2016-02-24 9:38 ` Tian, Kevin
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