* [PATCH v2 00/26] Add support for GuC-based SLPC
@ 2016-03-09 0:34 tom.orourke
2016-03-09 0:34 ` [PATCH 01/26] drm/i915/slpc: Expose guc functions for use with SLPC tom.orourke
` (26 more replies)
0 siblings, 27 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Tom O'Rourke <Tom.O'Rourke@intel.com>
SLPC (Single Loop Power Controller) is a replacement for
some host-based power management features. The SLPC
implemenation runs in firmware on GuC.
This series has been tested with SKL guc firmware
version 6.1 and BXT guc version 5.1.
The graphics power management features in SLPC in those
versions are called GTPERF, BALANCER, and DCC.
GTPERF is a combination of DFPS (Dynamic FPS) and Turbo.
DFPS adjusts requested graphics frequency to maintain
target framerate. Turbo adjusts requested graphics
frequency to maintain target GT busyness; this includes
an adaptive boost turbo method.
BALANCER adjusts balance between power budgets for IA
and GT in power limited scenarios. BALANCER is only
active when all display pipes are in "game" mode.
DCC (Duty Cycle Control) adjusts requested graphics
frequency and stalls guc-scheduler to maintain actual
graphics frequency in efficient range.
This series is a followup to the request for comments
"[Intel-gfx] [RFC 00/22] Add support for GuC-based SLPC"
https://lists.freedesktop.org/archives/intel-gfx/2016-January/085830.html
Thank you to Paulo for his valuable review of the RFC
series. Thank you also to Ville, Daniel, Jesse, and
Martin for their helpful comments.
We (Tom and Sagar) have attempted to incorporate these
suggestions in this series. We also adapted to a new
SLPC interface version that reflects an internal
reorganization within the firmware. The biggest change
refactored the tasks. The DFPS and Turbo tasks were
merged into the GTPERF task. The IBC (Intelligent Bias
Control) feature that had been grouped with Turbo was
split out into the BALANCER task.
The requested frequency can be fixed by setting min and
max to the same value. As before, the actual frequency
is controlled by the punit.
In addition to the debugfs files to enable/disable each
task, there is a module parameter to completely disable
SLPC. By default, SLPC will be disabled by module parameter.
Benchmarks showing power/performance results are expected
before enabling SLPC by default.
We anticipate DFPS and BALANCER will not be effective on
Linux systems due to difficulty determining frame rate
with a compositor and display not in "game" mode.
GTPERF (Turbo) and DCC should be effective.
Patches 22/26 to 26/26 are included for convenience in
testing this series and are not intended to be merged at
this time. SLPC requires guc submission and should be
disabled if guc submission is not enabled.
VIZ-6773, VIZ-6889
Dave Gordon (1):
DO NOT MERGE: drm/i915: Enable GuC submission, where supported
Peter Antoine (1):
DO NOT MERGE: drm/i915: resize the GuC WOPCM for rc6
Sagar Arun Kamble (3):
drm/i915/slpc: Add Display mode event related data structures
drm/i915/slpc: Notification of Display mode change
drm/i915/slpc: Notification of Refresh Rate change
Tom O'Rourke (21):
drm/i915/slpc: Expose guc functions for use with SLPC
drm/i915/slpc: Add has_slpc capability flag
drm/i915/slpc: Add slpc_version_check
drm/i915/slpc: Add enable_slpc module parameter
drm/i915/slpc: Use intel_slpc_* functions if supported
drm/i915/slpc: Enable SLPC in guc if supported
drm/i915/slpc: If using SLPC, do not set frequency
drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
drm/i915/slpc: Setup rps frequency values during SLPC init
drm/i915/slpc: Update current requested frequency
drm/i915/slpc: Send reset event
drm/i915/slpc: Send shutdown event
drm/i915/slpc: Add slpc_status enum values
drm/i915/slpc: Add parameter unset/set/get functions
drm/i915/slpc: Add slpc support for max/min freq
drm/i915/slpc: Add enable/disable debugfs for slpc
drm/i915/slpc: Add broxton support
drm/i915/slpc: Add i915_slpc_info to debugfs
DO NOT MERGE: drm/i915: Change SKL guc version wanted to 6.0
DO NOT MERGE: drm/i915/bxt: Add Broxton to guc loader
DO NOT MERGE: drm/i915: Enable SLPC, where supported
drivers/gpu/drm/i915/Makefile | 5 +-
drivers/gpu/drm/i915/i915_debugfs.c | 456 +++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_drv.c | 2 +
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_guc_reg.h | 3 +-
drivers/gpu/drm/i915/i915_guc_submission.c | 6 +-
drivers/gpu/drm/i915/i915_params.c | 10 +-
drivers/gpu/drm/i915/i915_params.h | 1 +
drivers/gpu/drm/i915/i915_sysfs.c | 20 ++
drivers/gpu/drm/i915/intel_display.c | 2 +
drivers/gpu/drm/i915/intel_dp.c | 2 +
drivers/gpu/drm/i915/intel_drv.h | 12 +
drivers/gpu/drm/i915/intel_guc.h | 13 +
drivers/gpu/drm/i915/intel_guc_loader.c | 53 +++-
drivers/gpu/drm/i915/intel_pm.c | 41 ++-
drivers/gpu/drm/i915/intel_slpc.c | 484 +++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_slpc.h | 209 +++++++++++++
17 files changed, 1299 insertions(+), 22 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
create mode 100644 drivers/gpu/drm/i915/intel_slpc.h
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 01/26] drm/i915/slpc: Expose guc functions for use with SLPC
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 02/26] drm/i915/slpc: Add has_slpc capability flag tom.orourke
` (25 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Tom O'Rourke <Tom.O'Rourke@intel.com>
Expose host2guc_action for use by SLPC in intel_slpc.c.
Expose functions to allocate and release objects used
by GuC to be used for SLPC shared memory object.
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/i915_guc_submission.c | 6 +++---
drivers/gpu/drm/i915/intel_guc.h | 4 ++++
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index d7543ef..33567c9 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -75,7 +75,7 @@ static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
return GUC2HOST_IS_RESPONSE(val);
}
-static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
+int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
u32 status;
@@ -609,7 +609,7 @@ int i915_guc_submit(struct i915_guc_client *client,
*
* Return: A drm_i915_gem_object if successful, otherwise NULL.
*/
-static struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device *dev,
+struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device *dev,
u32 size)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -640,7 +640,7 @@ static struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device *dev,
* gem_release_guc_obj() - Release gem object allocated for GuC usage
* @obj: gem obj to be released
*/
-static void gem_release_guc_obj(struct drm_i915_gem_object *obj)
+void gem_release_guc_obj(struct drm_i915_gem_object *obj)
{
if (!obj)
return;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 73002e9..b18f5c3 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -119,10 +119,14 @@ extern int intel_guc_suspend(struct drm_device *dev);
extern int intel_guc_resume(struct drm_device *dev);
/* i915_guc_submission.c */
+int host2guc_action(struct intel_guc *guc, u32 *data, u32 len);
int i915_guc_submission_init(struct drm_device *dev);
int i915_guc_submission_enable(struct drm_device *dev);
int i915_guc_submit(struct i915_guc_client *client,
struct drm_i915_gem_request *rq);
+struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device *dev,
+ u32 size);
+void gem_release_guc_obj(struct drm_i915_gem_object *obj);
void i915_guc_submission_disable(struct drm_device *dev);
void i915_guc_submission_fini(struct drm_device *dev);
int i915_guc_wq_check_space(struct i915_guc_client *client);
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 02/26] drm/i915/slpc: Add has_slpc capability flag
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
2016-03-09 0:34 ` [PATCH 01/26] drm/i915/slpc: Expose guc functions for use with SLPC tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 03/26] drm/i915/slpc: Add slpc_version_check tom.orourke
` (24 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Tom O'Rourke <Tom.O'Rourke@intel.com>
Add has_slpc capablity flag to indicate GuC firmware
supports single loop power control (SLPC). SLPC is
a replacement for some host-based power management
features.
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f37ac12..650d150 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -778,6 +778,7 @@ struct intel_csr {
func(is_kabylake) sep \
func(is_preliminary) sep \
func(has_fbc) sep \
+ func(has_slpc) sep \
func(has_pipe_cxsr) sep \
func(has_hotplug) sep \
func(cursor_needs_physical) sep \
@@ -2694,6 +2695,7 @@ struct drm_i915_cmd_table {
#define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
#define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
+#define HAS_SLPC(dev) (INTEL_INFO(dev)->has_slpc)
#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
INTEL_INFO(dev)->gen >= 8)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 03/26] drm/i915/slpc: Add slpc_version_check
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
2016-03-09 0:34 ` [PATCH 01/26] drm/i915/slpc: Expose guc functions for use with SLPC tom.orourke
2016-03-09 0:34 ` [PATCH 02/26] drm/i915/slpc: Add has_slpc capability flag tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 04/26] drm/i915/slpc: Add enable_slpc module parameter tom.orourke
` (23 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Tom O'Rourke <Tom.O'Rourke@intel.com>
The SLPC interface has changed and could continue to
change. Only GuC versions known to be compatible are
supported here.
On Skylake, GuC firmware v6 is supported. Other
platforms and versions can be added here later.
This patch also adds has_slpc to skylake info.
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/intel_guc_loader.c | 13 +++++++++++++
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 20e8200..a23d673 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -324,6 +324,7 @@ static const struct intel_device_info intel_skylake_info = {
HSW_FEATURES,
.is_skylake = 1,
.gen = 9,
+ .has_slpc = 1,
};
static const struct intel_device_info intel_skylake_gt3_info = {
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 82a3c03..22d7587 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -116,6 +116,17 @@ static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
I915_WRITE(GUC_WD_VECS_IER, ~irqs);
}
+static void slpc_version_check(struct drm_device *dev, struct intel_guc_fw *guc_fw)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_device_info *info;
+
+ if (IS_SKYLAKE(dev) && (guc_fw->guc_fw_major_found != 6)) {
+ info = (struct intel_device_info *) &dev_priv->info;
+ info->has_slpc = 0;
+ }
+}
+
static u32 get_gttype(struct drm_i915_private *dev_priv)
{
/* XXX: GT type based on PCI device ID? field seems unused by fw */
@@ -538,6 +549,8 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+ slpc_version_check(dev, guc_fw);
+
mutex_lock(&dev->struct_mutex);
obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
mutex_unlock(&dev->struct_mutex);
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 04/26] drm/i915/slpc: Add enable_slpc module parameter
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (2 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 03/26] drm/i915/slpc: Add slpc_version_check tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 05/26] drm/i915/slpc: Use intel_slpc_* functions if supported tom.orourke
` (22 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Tom O'Rourke <Tom.O'Rourke@intel.com>
i915.enable_slpc is used to override the default for slpc usage.
The expected values are -1=auto, 0=disabled [default], 1=enabled.
slpc_enable_sanitize() converts i915.enable_slpc to either 0 or 1.
Interpretation of default value is based on HAS_SLPC(), after
slpc_version_check(). This function also enforces the requirement
that guc_submission is required for slpc.
intel_slpc_enabled() returns 1 if SLPC should be used.
Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/i915_params.c | 6 ++++++
drivers/gpu/drm/i915/i915_params.h | 1 +
drivers/gpu/drm/i915/intel_guc.h | 6 ++++++
drivers/gpu/drm/i915/intel_guc_loader.c | 17 +++++++++++++++++
4 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 278c9c4..1cee0ea 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -36,6 +36,7 @@ struct i915_params i915 __read_mostly = {
.enable_dc = -1,
.enable_fbc = -1,
.enable_execlists = -1,
+ .enable_slpc = 0,
.enable_hangcheck = true,
.enable_ppgtt = -1,
.enable_psr = -1,
@@ -125,6 +126,11 @@ MODULE_PARM_DESC(enable_execlists,
"Override execlists usage. "
"(-1=auto [default], 0=disabled, 1=enabled)");
+module_param_named_unsafe(enable_slpc, i915.enable_slpc, int, 0400);
+MODULE_PARM_DESC(enable_slpc,
+ "Override single-loop-power-controller (slpc) usage. "
+ "(-1=auto, 0=disabled [default], 1=enabled)");
+
module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
MODULE_PARM_DESC(enable_psr, "Enable PSR "
"(0=disabled, 1=enabled - link mode chosen per-platform, 2=force link-standby mode, 3=force link-off mode) "
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index bd5026b..3de9fb8 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -39,6 +39,7 @@ struct i915_params {
int enable_fbc;
int enable_ppgtt;
int enable_execlists;
+ int enable_slpc;
int enable_psr;
unsigned int preliminary_hw_support;
int disable_power_well;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index b18f5c3..298e243 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -110,6 +110,12 @@ struct intel_guc {
uint32_t last_seqno[GUC_MAX_ENGINES_NUM];
};
+static inline int intel_slpc_enabled(void)
+{
+ WARN_ON(i915.enable_slpc < 0);
+ return i915.enable_slpc;
+}
+
/* intel_guc_loader.c */
extern void intel_guc_ucode_init(struct drm_device *dev);
extern int intel_guc_ucode_load(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 22d7587..d63f358 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -116,6 +116,21 @@ static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
I915_WRITE(GUC_WD_VECS_IER, ~irqs);
}
+static void slpc_enable_sanitize(struct drm_device *dev)
+{
+ /* handle default case */
+ if (i915.enable_slpc < 0)
+ i915.enable_slpc = HAS_SLPC(dev);
+
+ /* slpc requires hardware support and compatible firmware */
+ if (!HAS_SLPC(dev))
+ i915.enable_slpc = 0;
+
+ /* slpc requires guc submission */
+ if (!i915.enable_guc_submission)
+ i915.enable_slpc = 0;
+}
+
static void slpc_version_check(struct drm_device *dev, struct intel_guc_fw *guc_fw)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -125,6 +140,8 @@ static void slpc_version_check(struct drm_device *dev, struct intel_guc_fw *guc_
info = (struct intel_device_info *) &dev_priv->info;
info->has_slpc = 0;
}
+
+ slpc_enable_sanitize(dev);
}
static u32 get_gttype(struct drm_i915_private *dev_priv)
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 05/26] drm/i915/slpc: Use intel_slpc_* functions if supported
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (3 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 04/26] drm/i915/slpc: Add enable_slpc module parameter tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 06/26] drm/i915/slpc: Enable SLPC in guc " tom.orourke
` (21 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Tom O'Rourke <Tom.O'Rourke@intel.com>
On platforms with SLPC support: call intel_slpc_*()
functions from corresponding intel_*_gt_powersave()
functions; and do not use rps functions.
v2: return void instead of ignored error code (Paulo)
enable/disable RC6 in SLPC flows (Sagar)
replace HAS_SLPC() use with intel_slpc_enabled()
or intel_slpc_active() (Paulo)
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/Makefile | 5 ++--
drivers/gpu/drm/i915/intel_drv.h | 4 +++
drivers/gpu/drm/i915/intel_guc.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 36 ++++++++++++++++++-------
drivers/gpu/drm/i915/intel_slpc.c | 56 +++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_slpc.h | 35 ++++++++++++++++++++++++
6 files changed, 126 insertions(+), 11 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
create mode 100644 drivers/gpu/drm/i915/intel_slpc.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0851de07..92b378b 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -41,8 +41,9 @@ i915-y += i915_cmd_parser.o \
intel_uncore.o
# general-purpose microcontroller (GuC) support
-i915-y += intel_guc_loader.o \
- i915_guc_submission.o
+i915-y += i915_guc_submission.o \
+ intel_guc_loader.o \
+ intel_slpc.o
# autogenerated null render state
i915-y += intel_renderstate_gen6.o \
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3daf1e3..11e7d66 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1587,6 +1587,10 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
enum dpio_channel ch, bool override);
+static inline int intel_slpc_active(struct drm_device *dev)
+{
+ return 0;
+}
/* intel_pm.c */
void intel_init_clock_gating(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 298e243..417cc82 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -26,6 +26,7 @@
#include "intel_guc_fwif.h"
#include "i915_guc_reg.h"
+#include "intel_slpc.h"
struct i915_guc_client {
struct drm_i915_gem_object *client_obj;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f65e841..9820a77 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6178,7 +6178,9 @@ void intel_init_gt_powersave(struct drm_device *dev)
intel_runtime_pm_get(dev_priv);
}
- if (IS_CHERRYVIEW(dev))
+ if (intel_slpc_enabled())
+ intel_slpc_init(dev);
+ else if (IS_CHERRYVIEW(dev))
cherryview_init_gt_powersave(dev);
else if (IS_VALLEYVIEW(dev))
valleyview_init_gt_powersave(dev);
@@ -6188,7 +6190,9 @@ void intel_cleanup_gt_powersave(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- if (IS_CHERRYVIEW(dev))
+ if (intel_slpc_active(dev))
+ intel_slpc_cleanup(dev);
+ else if (IS_CHERRYVIEW(dev))
return;
else if (IS_VALLEYVIEW(dev))
valleyview_cleanup_gt_powersave(dev);
@@ -6221,17 +6225,24 @@ void intel_suspend_gt_powersave(struct drm_device *dev)
if (INTEL_INFO(dev)->gen < 6)
return;
- gen6_suspend_rps(dev);
+ if (intel_slpc_active(dev)) {
+ intel_slpc_suspend(dev);
+ } else {
+ gen6_suspend_rps(dev);
- /* Force GPU to min freq during suspend */
- gen6_rps_idle(dev_priv);
+ /* Force GPU to min freq during suspend */
+ gen6_rps_idle(dev_priv);
+ }
}
void intel_disable_gt_powersave(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- if (IS_IRONLAKE_M(dev)) {
+ if (intel_slpc_active(dev)) {
+ intel_slpc_disable(dev);
+ gen9_disable_rps(dev);
+ } else if (IS_IRONLAKE_M(dev)) {
ironlake_disable_drps(dev);
} else if (INTEL_INFO(dev)->gen >= 6) {
intel_suspend_gt_powersave(dev);
@@ -6302,7 +6313,10 @@ void intel_enable_gt_powersave(struct drm_device *dev)
if (intel_vgpu_active(dev))
return;
- if (IS_IRONLAKE_M(dev)) {
+ if (intel_slpc_active(dev)) {
+ gen9_enable_rc6(dev);
+ intel_slpc_enable(dev);
+ } else if (IS_IRONLAKE_M(dev)) {
ironlake_enable_drps(dev);
mutex_lock(&dev->struct_mutex);
intel_init_emon(dev);
@@ -6333,8 +6347,12 @@ void intel_reset_gt_powersave(struct drm_device *dev)
if (INTEL_INFO(dev)->gen < 6)
return;
- gen6_suspend_rps(dev);
- dev_priv->rps.enabled = false;
+ if (intel_slpc_active(dev)) {
+ intel_slpc_reset(dev);
+ } else {
+ gen6_suspend_rps(dev);
+ dev_priv->rps.enabled = false;
+ }
}
static void ibx_init_clock_gating(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
new file mode 100644
index 0000000..474fac0
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#include <linux/firmware.h>
+#include "i915_drv.h"
+#include "intel_guc.h"
+
+void intel_slpc_init(struct drm_device *dev)
+{
+ return;
+}
+
+void intel_slpc_cleanup(struct drm_device *dev)
+{
+ return;
+}
+
+void intel_slpc_suspend(struct drm_device *dev)
+{
+ return;
+}
+
+void intel_slpc_disable(struct drm_device *dev)
+{
+ return;
+}
+
+void intel_slpc_enable(struct drm_device *dev)
+{
+ return;
+}
+
+void intel_slpc_reset(struct drm_device *dev)
+{
+ return;
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
new file mode 100644
index 0000000..6cfadb3
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#ifndef _INTEL_SLPC_H_
+#define _INTEL_SLPC_H_
+
+/* intel_slpc.c */
+void intel_slpc_init(struct drm_device *dev);
+void intel_slpc_cleanup(struct drm_device *dev);
+void intel_slpc_suspend(struct drm_device *dev);
+void intel_slpc_disable(struct drm_device *dev);
+void intel_slpc_enable(struct drm_device *dev);
+void intel_slpc_reset(struct drm_device *dev);
+
+#endif
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 06/26] drm/i915/slpc: Enable SLPC in guc if supported
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (4 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 05/26] drm/i915/slpc: Use intel_slpc_* functions if supported tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 07/26] drm/i915/slpc: If using SLPC, do not set frequency tom.orourke
` (20 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Tom O'Rourke <Tom.O'Rourke@intel.com>
If slpc enabled, then add enable SLPC flag to guc
control parameter during guc load.
v2: Use intel_slpc_enabled() (Paulo)
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/intel_guc_loader.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index d63f358..a3848bf 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -187,6 +187,9 @@ static void set_guc_init_params(struct drm_i915_private *dev_priv)
params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
GUC_CTL_VCS2_ENABLED;
+ if (intel_slpc_enabled())
+ params[GUC_CTL_FEATURE] |= GUC_CTL_ENABLE_SLPC;
+
if (i915.guc_log_level >= 0) {
params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
params[GUC_CTL_DEBUG] =
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 07/26] drm/i915/slpc: If using SLPC, do not set frequency
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (5 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 06/26] drm/i915/slpc: Enable SLPC in guc " tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 08/26] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data tom.orourke
` (19 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Tom O'Rourke <Tom.O'Rourke@intel.com>
When frequency requests are made by SLPC, host driver
should not attempt to make frequency requests due to
potential conflicts.
Host-based turbo operations are already avoided when
SLPC is used. This change covers other frequency
requests such as from sysfs or debugfs interfaces.
A later patch in this series updates sysfs/debugfs
interfaces for setting max/min frequencies with SLPC.
v2: Use intel_slpc_active instead of HAS_SLPC (Paulo)
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9820a77..05db63a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4564,6 +4564,9 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv,
void intel_set_rps(struct drm_device *dev, u8 val)
{
+ if (intel_slpc_active(dev))
+ return;
+
if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
valleyview_set_rps(dev, val);
else
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 08/26] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (6 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 07/26] drm/i915/slpc: If using SLPC, do not set frequency tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 09/26] drm/i915/slpc: Setup rps frequency values during SLPC init tom.orourke
` (18 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Tom O'Rourke <Tom.O'Rourke@intel.com>
SLPC shared data is used to pass information
to/from SLPC firmware.
For Skylake, platform sku type and slice count
are identified from device id and fuse values.
Support for other platforms needs to be added.
v2: Update for SLPC interface version 2015.2.4
intel_slpc_active() returns 1 if slpc initialized (Paulo)
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/intel_drv.h | 9 ++++-
drivers/gpu/drm/i915/intel_guc.h | 2 +
drivers/gpu/drm/i915/intel_slpc.c | 84 ++++++++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_slpc.h | 75 ++++++++++++++++++++++++++++++++++
4 files changed, 167 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 11e7d66..724c482 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1589,9 +1589,16 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
static inline int intel_slpc_active(struct drm_device *dev)
{
- return 0;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int ret = 0;
+
+ if (dev_priv->guc.slpc.shared_data_obj)
+ ret = 1;
+
+ return ret;
}
+
/* intel_pm.c */
void intel_init_clock_gating(struct drm_device *dev);
void intel_suspend_hw(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 417cc82..62075db 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -109,6 +109,8 @@ struct intel_guc {
uint64_t submissions[GUC_MAX_ENGINES_NUM];
uint32_t last_seqno[GUC_MAX_ENGINES_NUM];
+
+ struct intel_slpc slpc;
};
static inline int intel_slpc_enabled(void)
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 474fac0..4689e70 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -22,17 +22,97 @@
*
*/
#include <linux/firmware.h>
+#include <asm/msr-index.h>
#include "i915_drv.h"
#include "intel_guc.h"
+static u8 slpc_get_platform_sku(struct drm_i915_gem_object *obj)
+{
+ struct drm_device *dev = obj->base.dev;
+ enum slpc_platform_sku platform_sku;
+
+ if (IS_SKL_ULX(dev))
+ platform_sku = SLPC_PLATFORM_SKU_ULX;
+ else if (IS_SKL_ULT(dev))
+ platform_sku = SLPC_PLATFORM_SKU_ULT;
+ else
+ platform_sku = SLPC_PLATFORM_SKU_DT;
+
+ return (u8) platform_sku;
+}
+
+static u8 slpc_get_slice_count(struct drm_i915_gem_object *obj)
+{
+ struct drm_device *dev = obj->base.dev;
+ u8 slice_count = 1;
+
+ if (IS_SKYLAKE(dev))
+ slice_count = INTEL_INFO(dev)->slice_total;
+
+ return slice_count;
+}
+
+static void slpc_shared_data_init(struct drm_i915_gem_object *obj)
+{
+ struct page *page;
+ struct slpc_shared_data *data;
+ u64 msr_value;
+
+ page = i915_gem_object_get_page(obj, 0);
+ if (page) {
+ data = kmap_atomic(page);
+ memset(data, 0, sizeof(struct slpc_shared_data));
+
+ data->slpc_version = SLPC_VERSION;
+ data->shared_data_size = sizeof(struct slpc_shared_data);
+ data->global_state = (u32) SLPC_GLOBAL_STATE_NOT_RUNNING;
+ data->platform_info.platform_sku = slpc_get_platform_sku(obj);
+ data->platform_info.slice_count = slpc_get_slice_count(obj);
+ data->platform_info.host_os = (u8) SLPC_HOST_OS_UNDEFINED;
+ data->platform_info.power_plan_source =
+ (u8) SLPC_POWER_PLAN_SOURCE(SLPC_POWER_PLAN_BALANCED,
+ SLPC_POWER_SOURCE_AC);
+ rdmsrl(MSR_TURBO_RATIO_LIMIT, msr_value);
+ data->platform_info.P0_freq = (u8) msr_value;
+ rdmsrl(MSR_PLATFORM_INFO, msr_value);
+ data->platform_info.P1_freq = (u8) (msr_value >> 8);
+ data->platform_info.Pe_freq = (u8) (msr_value >> 40);
+ data->platform_info.Pn_freq = (u8) (msr_value >> 48);
+ rdmsrl(MSR_PKG_POWER_LIMIT, msr_value);
+ data->platform_info.package_rapl_limit_high =
+ (u32) (msr_value >> 32);
+ data->platform_info.package_rapl_limit_low = (u32) msr_value;
+
+ kunmap_atomic(data);
+ }
+}
+
void intel_slpc_init(struct drm_device *dev)
{
- return;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_gem_object *obj;
+
+ /* Allocate shared data structure */
+ obj = dev_priv->guc.slpc.shared_data_obj;
+ if (!obj) {
+ obj = gem_allocate_guc_obj(dev_priv->dev,
+ PAGE_ALIGN(sizeof(struct slpc_shared_data)));
+ dev_priv->guc.slpc.shared_data_obj = obj;
+ }
+
+ if (!obj)
+ DRM_ERROR("slpc_shared_data allocation failed\n");
+ else
+ slpc_shared_data_init(obj);
}
void intel_slpc_cleanup(struct drm_device *dev)
{
- return;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ /* Release shared data sturcutre */
+ gem_release_guc_obj(dev_priv->guc.slpc.shared_data_obj);
+ dev_priv->guc.slpc.shared_data_obj = NULL;
}
void intel_slpc_suspend(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 6cfadb3..94cd2f4 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -24,6 +24,81 @@
#ifndef _INTEL_SLPC_H_
#define _INTEL_SLPC_H_
+#define SLPC_MAJOR_VER 2
+#define SLPC_MINOR_VER 4
+#define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
+
+enum slpc_global_state {
+ SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
+ SLPC_GLOBAL_STATE_INITIALIZING = 1,
+ SLPC_GLOBAL_STATE_RESETING = 2,
+ SLPC_GLOBAL_STATE_RUNNING = 3,
+ SLPC_GLOBAL_STATE_SHUTTING_DOWN = 4,
+ SLPC_GLOBAL_STATE_ERROR = 5
+};
+
+enum slpc_host_os {
+ SLPC_HOST_OS_UNDEFINED = 0,
+ SLPC_HOST_OS_WINDOWS_8 = 1,
+};
+
+enum slpc_platform_sku {
+ SLPC_PLATFORM_SKU_UNDEFINED = 0,
+ SLPC_PLATFORM_SKU_ULX = 1,
+ SLPC_PLATFORM_SKU_ULT = 2,
+ SLPC_PLATFORM_SKU_T = 3,
+ SLPC_PLATFORM_SKU_MOBL = 4,
+ SLPC_PLATFORM_SKU_DT = 5,
+ SLPC_PLATFORM_SKU_UNKNOWN = 6,
+};
+
+enum slpc_power_plan {
+ SLPC_POWER_PLAN_UNDEFINED = 0,
+ SLPC_POWER_PLAN_BATTERY_SAVER = 1,
+ SLPC_POWER_PLAN_BALANCED = 2,
+ SLPC_POWER_PLAN_PERFORMANCE = 3,
+ SLPC_POWER_PLAN_UNKNOWN = 4,
+};
+
+enum slpc_power_source {
+ SLPC_POWER_SOURCE_UNDEFINED = 0,
+ SLPC_POWER_SOURCE_AC = 1,
+ SLPC_POWER_SOURCE_DC = 2,
+ SLPC_POWER_SOURCE_UNKNOWN = 3,
+};
+
+#define SLPC_POWER_PLAN_SOURCE(plan, source) ((plan) | ((source) << 6))
+
+struct slpc_platform_info {
+ u8 platform_sku;
+ u8 slice_count;
+ u8 host_os;
+ u8 power_plan_source;
+ u8 P0_freq;
+ u8 P1_freq;
+ u8 Pe_freq;
+ u8 Pn_freq;
+ u32 package_rapl_limit_high;
+ u32 package_rapl_limit_low;
+} __packed;
+
+#define SLPC_MAX_OVERRIDE_PARAMETERS 192
+#define SLPC_OVERRIDE_BITFIELD_SIZE ((SLPC_MAX_OVERRIDE_PARAMETERS + 31) / 32)
+
+struct slpc_shared_data {
+ u32 slpc_version;
+ u32 shared_data_size;
+ u32 global_state;
+ struct slpc_platform_info platform_info;
+ u32 task_state_data;
+ u32 override_parameters_set_bits[SLPC_OVERRIDE_BITFIELD_SIZE];
+ u32 override_parameters_values[SLPC_MAX_OVERRIDE_PARAMETERS];
+} __packed;
+
+struct intel_slpc {
+ struct drm_i915_gem_object *shared_data_obj;
+};
+
/* intel_slpc.c */
void intel_slpc_init(struct drm_device *dev);
void intel_slpc_cleanup(struct drm_device *dev);
--
1.9.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 09/26] drm/i915/slpc: Setup rps frequency values during SLPC init
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (7 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 08/26] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 10/26] drm/i915/slpc: Update current requested frequency tom.orourke
` (17 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Tom O'Rourke <Tom.O'Rourke@intel.com>
v2: Add mutex lock/unlock
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 2 +-
drivers/gpu/drm/i915/intel_slpc.c | 5 +++++
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 724c482..f9670b9 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1608,6 +1608,7 @@ void intel_init_pm(struct drm_device *dev);
void intel_pm_setup(struct drm_device *dev);
void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
void intel_gpu_ips_teardown(void);
+void gen6_init_rps_frequencies(struct drm_device *dev);
void intel_init_gt_powersave(struct drm_device *dev);
void intel_cleanup_gt_powersave(struct drm_device *dev);
void intel_enable_gt_powersave(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 05db63a..e6dec97 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4712,7 +4712,7 @@ int intel_enable_rc6(const struct drm_device *dev)
return i915.enable_rc6;
}
-static void gen6_init_rps_frequencies(struct drm_device *dev)
+void gen6_init_rps_frequencies(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t rp_state_cap;
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 4689e70..3f9f56c 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -92,6 +92,11 @@ void intel_slpc_init(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_i915_gem_object *obj;
+ /* Initialize the rps frequecny values */
+ mutex_lock(&dev_priv->rps.hw_lock);
+ gen6_init_rps_frequencies(dev);
+ mutex_unlock(&dev_priv->rps.hw_lock);
+
/* Allocate shared data structure */
obj = dev_priv->guc.slpc.shared_data_obj;
if (!obj) {
--
1.9.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 10/26] drm/i915/slpc: Update current requested frequency
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (8 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 09/26] drm/i915/slpc: Setup rps frequency values during SLPC init tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 11/26] drm/i915/slpc: Send reset event tom.orourke
` (16 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Tom O'Rourke <Tom.O'Rourke@intel.com>
When SLPC is controlling requested frequency, the rps.cur_freq
value is not used to make the frequency request.
Before using rps.cur_freq in sysfs or debugfs, read
requested frequency from register to get the value
most recently requested by SLPC firmware.
v2: replace HAS_SLPC with intel_slpc_active (Paulo)
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++++
drivers/gpu/drm/i915/i915_sysfs.c | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 15aacd0..6bf9282 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1135,6 +1135,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
flush_delayed_work(&dev_priv->rps.delayed_resume_work);
+ if (intel_slpc_active(dev))
+ dev_priv->rps.cur_freq = (I915_READ(GEN6_RPNSWREQ) >> 23);
+
if (IS_GEN5(dev)) {
u16 rgvswctl = I915_READ16(MEMSWCTL);
u16 rgvstat = I915_READ16(MEMSTAT_ILK);
@@ -2351,6 +2354,9 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_file *file;
+ if (intel_slpc_active(dev))
+ dev_priv->rps.cur_freq = (I915_READ(GEN6_RPNSWREQ) >> 23);
+
seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 2d576b7..923a63a 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -318,6 +318,8 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
intel_runtime_pm_get(dev_priv);
mutex_lock(&dev_priv->rps.hw_lock);
+ if (intel_slpc_active(dev))
+ dev_priv->rps.cur_freq = (I915_READ(GEN6_RPNSWREQ) >> 23);
ret = intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq);
mutex_unlock(&dev_priv->rps.hw_lock);
--
1.9.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 11/26] drm/i915/slpc: Send reset event
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (9 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 10/26] drm/i915/slpc: Update current requested frequency tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 12/26] drm/i915/slpc: Send shutdown event tom.orourke
` (15 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Tom O'Rourke <Tom.O'Rourke@intel.com>
Add host2guc SLPC reset event and send reset event
during enable.
v2: extract host2guc_slpc to handle slpc status code
coding style changes (Paulo)
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/intel_slpc.c | 33 ++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_slpc.h | 14 ++++++++++++++
2 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 3f9f56c..c8a5cde 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -26,6 +26,36 @@
#include "i915_drv.h"
#include "intel_guc.h"
+static void host2guc_slpc(struct drm_i915_private *dev_priv, u32 *data, u32 len)
+{
+ int ret = host2guc_action(&dev_priv->guc, data, len);
+
+ if (!ret) {
+ ret = I915_READ(SOFT_SCRATCH(1));
+ ret &= SLPC_EVENT_STATUS_MASK;
+ }
+
+ if (ret)
+ DRM_ERROR("event 0x%x status %d\n", (data[1] >> 8), ret);
+}
+
+static void host2guc_slpc_reset(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_gem_object *obj = dev_priv->guc.slpc.shared_data_obj;
+ u32 data[4];
+ u64 shared_data_gtt_offset = i915_gem_obj_ggtt_offset(obj);
+
+ data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+ data[1] = SLPC_EVENT(SLPC_EVENT_RESET, 2);
+ data[2] = lower_32_bits(shared_data_gtt_offset);
+ data[3] = upper_32_bits(shared_data_gtt_offset);
+
+ WARN_ON(data[3] != 0);
+
+ host2guc_slpc(dev_priv, data, 4);
+}
+
static u8 slpc_get_platform_sku(struct drm_i915_gem_object *obj)
{
struct drm_device *dev = obj->base.dev;
@@ -132,7 +162,8 @@ void intel_slpc_disable(struct drm_device *dev)
void intel_slpc_enable(struct drm_device *dev)
{
- return;
+ if (intel_slpc_active(dev))
+ host2guc_slpc_reset(dev);
}
void intel_slpc_reset(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 94cd2f4..7f33a04 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -28,6 +28,20 @@
#define SLPC_MINOR_VER 4
#define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
+enum slpc_event_id {
+ SLPC_EVENT_RESET = 0,
+ SLPC_EVENT_SHUTDOWN = 1,
+ SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,
+ SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,
+ SLPC_EVENT_FLIP_COMPLETE = 4,
+ SLPC_EVENT_QUERY_TASK_STATE = 5,
+ SLPC_EVENT_PARAMETER_SET = 6,
+ SLPC_EVENT_PARAMETER_UNSET = 7,
+};
+
+#define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
+#define SLPC_EVENT_STATUS_MASK 0xFF
+
enum slpc_global_state {
SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
SLPC_GLOBAL_STATE_INITIALIZING = 1,
--
1.9.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 12/26] drm/i915/slpc: Send shutdown event
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (10 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 11/26] drm/i915/slpc: Send reset event tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 13/26] drm/i915/slpc: Add Display mode event related data structures tom.orourke
` (14 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Tom O'Rourke <Tom.O'Rourke@intel.com>
Send SLPC shutdown event during disable, suspend, and reset
operations. Sending shutdown event while already shutdown
is OK.
v2: return void instead of ignored error code (Paulo)
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/intel_slpc.c | 28 +++++++++++++++++++++++++---
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index c8a5cde..b6ba071 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -56,6 +56,23 @@ static void host2guc_slpc_reset(struct drm_device *dev)
host2guc_slpc(dev_priv, data, 4);
}
+static void host2guc_slpc_shutdown(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_gem_object *obj = dev_priv->guc.slpc.shared_data_obj;
+ u32 data[4];
+ u64 shared_data_gtt_offset = i915_gem_obj_ggtt_offset(obj);
+
+ data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+ data[1] = SLPC_EVENT(SLPC_EVENT_SHUTDOWN, 2);
+ data[2] = lower_32_bits(shared_data_gtt_offset);
+ data[3] = upper_32_bits(shared_data_gtt_offset);
+
+ WARN_ON(0 != data[3]);
+
+ host2guc_slpc(dev_priv, data, 4);
+}
+
static u8 slpc_get_platform_sku(struct drm_i915_gem_object *obj)
{
struct drm_device *dev = obj->base.dev;
@@ -152,12 +169,14 @@ void intel_slpc_cleanup(struct drm_device *dev)
void intel_slpc_suspend(struct drm_device *dev)
{
- return;
+ if (intel_slpc_active(dev))
+ host2guc_slpc_shutdown(dev);
}
void intel_slpc_disable(struct drm_device *dev)
{
- return;
+ if (intel_slpc_active(dev))
+ host2guc_slpc_shutdown(dev);
}
void intel_slpc_enable(struct drm_device *dev)
@@ -168,5 +187,8 @@ void intel_slpc_enable(struct drm_device *dev)
void intel_slpc_reset(struct drm_device *dev)
{
- return;
+ if (intel_slpc_active(dev)) {
+ host2guc_slpc_shutdown(dev);
+ host2guc_slpc_reset(dev);
+ }
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 13/26] drm/i915/slpc: Add Display mode event related data structures
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (11 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 12/26] drm/i915/slpc: Send shutdown event tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 14/26] drm/i915/slpc: Notification of Display mode change tom.orourke
` (13 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni
From: Sagar Arun Kamble <sagar.a.kamble@intel.com>
v2: Cleaning up defines for number of pipes and other cosmetic changes.
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Acked-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/intel_slpc.h | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 7f33a04..b963fe7 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -109,8 +109,37 @@ struct slpc_shared_data {
u32 override_parameters_values[SLPC_MAX_OVERRIDE_PARAMETERS];
} __packed;
+#define SLPC_MAX_NUM_OF_PIPES 4
+
+struct intel_display_pipe_info {
+ union {
+ u32 data;
+ struct {
+ u32 is_widi:1;
+ u32 refresh_rate:7;
+ u32 vsync_ft_usec:24;
+ };
+ };
+} __packed;
+
+struct intel_slpc_display_mode_event_params {
+ struct {
+ struct intel_display_pipe_info per_pipe_info[SLPC_MAX_NUM_OF_PIPES];
+ union {
+ u32 global_data;
+ struct {
+ u32 active_pipes_bitmask:SLPC_MAX_NUM_OF_PIPES;
+ u32 fullscreen_pipes:SLPC_MAX_NUM_OF_PIPES;
+ u32 vbi_sync_on_pipes:SLPC_MAX_NUM_OF_PIPES;
+ u32 num_active_pipes:2;
+ };
+ };
+ };
+} __packed;
+
struct intel_slpc {
struct drm_i915_gem_object *shared_data_obj;
+ struct intel_slpc_display_mode_event_params display_mode_params;
};
/* intel_slpc.c */
--
1.9.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 14/26] drm/i915/slpc: Notification of Display mode change
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (12 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 13/26] drm/i915/slpc: Add Display mode event related data structures tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 15/26] drm/i915/slpc: Notification of Refresh Rate change tom.orourke
` (12 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Sagar Arun Kamble <sagar.a.kamble@intel.com>
GuC SLPC need to be sent data related to Active pipes, refresh rates,
widi pipes, fullscreen pipes related via host to GuC display mode
change event. Based on this, SLPC will track FPS on active pipes.
This patch defines the event and implements trigger of the event.
v2: Addressed review comments from Paulo and Ville. Changed the way
display mode information is collected in intel_atomic_commit. Coupled
display mode change event with SLPC enable/reset event. Updated inactive
crtc state in display mode data. Updated refresh rate and vsync_ft_usec
calculations to get more accurate value. (Paulo)
v2(torourke): Updates suggested by Paulo: replace HAS_SLPC with
intel_slpc_active. return void instead of ignored error code.
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 +
drivers/gpu/drm/i915/intel_slpc.c | 142 ++++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_slpc.h | 3 +
3 files changed, 146 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 62d36a7..ac398f3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13820,6 +13820,8 @@ static int intel_atomic_commit(struct drm_device *dev,
if (hw_check)
intel_modeset_check_state(dev, state);
+ intel_slpc_update_atomic_commit_info(dev, state);
+
drm_atomic_state_free(state);
/* As one of the primary mmio accessors, KMS has a high likelihood
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index b6ba071..58f90b3 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -73,6 +73,21 @@ static void host2guc_slpc_shutdown(struct drm_device *dev)
host2guc_slpc(dev_priv, data, 4);
}
+static void host2guc_slpc_display_mode_change(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 data[7];
+ int i;
+
+ data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+ data[1] = SLPC_EVENT(SLPC_EVENT_DISPLAY_MODE_CHANGE, SLPC_MAX_NUM_OF_PIPES + 1);
+ data[2] = dev_priv->guc.slpc.display_mode_params.global_data;
+ for(i = 0; i < SLPC_MAX_NUM_OF_PIPES; ++i)
+ data[3+i] = dev_priv->guc.slpc.display_mode_params.per_pipe_info[i].data;
+
+ host2guc_slpc(dev_priv, data, 7);
+}
+
static u8 slpc_get_platform_sku(struct drm_i915_gem_object *obj)
{
struct drm_device *dev = obj->base.dev;
@@ -181,8 +196,10 @@ void intel_slpc_disable(struct drm_device *dev)
void intel_slpc_enable(struct drm_device *dev)
{
- if (intel_slpc_active(dev))
+ if (intel_slpc_active(dev)) {
host2guc_slpc_reset(dev);
+ intel_slpc_update_display_mode_info(dev);
+ }
}
void intel_slpc_reset(struct drm_device *dev)
@@ -192,3 +209,126 @@ void intel_slpc_reset(struct drm_device *dev)
host2guc_slpc_reset(dev);
}
}
+
+void intel_slpc_update_display_mode_info(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc;
+ struct intel_display_pipe_info *per_pipe_info;
+ struct intel_slpc_display_mode_event_params *cur_params, old_params;
+ bool notify = false;
+
+ if (!intel_slpc_active(dev))
+ return;
+
+ /* Copy display mode parameters for comparison */
+ cur_params = &dev_priv->guc.slpc.display_mode_params;
+ old_params.global_data = cur_params->global_data;
+ cur_params->global_data = 0;
+
+ intel_runtime_pm_get(dev_priv);
+ drm_modeset_lock_all(dev);
+
+ for_each_intel_crtc(dev, intel_crtc) {
+ per_pipe_info = &cur_params->per_pipe_info[intel_crtc->pipe];
+ old_params.per_pipe_info[intel_crtc->pipe].data = per_pipe_info->data;
+ per_pipe_info->data = 0;
+
+ if (intel_crtc->active) {
+ struct drm_display_mode *mode = &intel_crtc->base.mode;
+ /* FIXME: Update is_widi based on encoder */
+ per_pipe_info->is_widi = 0;
+ per_pipe_info->refresh_rate =
+ (mode->clock * 1000)/ (mode->htotal * mode->vtotal);
+ if (!per_pipe_info->refresh_rate) {
+ DRM_ERROR("Invalid mode refresh rate\n");
+ drm_modeset_unlock_all(dev);
+ intel_runtime_pm_put(dev_priv);
+ return;
+ }
+ per_pipe_info->vsync_ft_usec =
+ (mode->htotal * mode->vtotal * 1000) / mode->clock;
+ cur_params->active_pipes_bitmask |= (1 << intel_crtc->pipe);
+ cur_params->vbi_sync_on_pipes |= (1 << intel_crtc->pipe);
+ } else {
+ cur_params->active_pipes_bitmask &= (0 << intel_crtc->pipe);
+ cur_params->vbi_sync_on_pipes &= (0 << intel_crtc->pipe);
+ }
+
+ if (old_params.per_pipe_info[intel_crtc->pipe].data != per_pipe_info->data)
+ notify = true;
+ }
+
+ drm_modeset_unlock_all(dev);
+
+ cur_params->num_active_pipes = hweight32(cur_params->active_pipes_bitmask);
+
+ /* Compare old display mode with current mode. Notify SLPC if it is changed. */
+ if (cur_params->global_data != old_params.global_data)
+ notify = true;
+
+ if (notify) {
+ host2guc_slpc_display_mode_change(dev);
+ }
+
+ intel_runtime_pm_put(dev_priv);
+}
+
+void intel_slpc_update_atomic_commit_info(struct drm_device *dev,
+ struct drm_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *crtc_state;
+ struct intel_display_pipe_info *per_pipe_info;
+ struct intel_slpc_display_mode_event_params *cur_params, old_params;
+ bool notify = false;
+ int i;
+
+ if (!intel_slpc_active(dev))
+ return;
+
+ /* Copy display mode parameters for comparison */
+ cur_params = &dev_priv->guc.slpc.display_mode_params;
+ old_params.global_data = cur_params->global_data;
+
+ for_each_crtc_in_state(state, crtc, crtc_state, i) {
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+ per_pipe_info = &cur_params->per_pipe_info[intel_crtc->pipe];
+ old_params.per_pipe_info[intel_crtc->pipe].data = per_pipe_info->data;
+
+ per_pipe_info->data = 0;
+ cur_params->active_pipes_bitmask &= (0 << intel_crtc->pipe);
+ cur_params->vbi_sync_on_pipes &= (0 << intel_crtc->pipe);
+
+ if (crtc_state->active) {
+ struct drm_display_mode *mode = &crtc->mode;
+ /* FIXME: Update is_widi based on encoder */
+ per_pipe_info->is_widi = 0;
+ per_pipe_info->refresh_rate =
+ (mode->clock * 1000)/ (mode->htotal * mode->vtotal);
+ if (!per_pipe_info->refresh_rate) {
+ DRM_ERROR("Invalid mode refresh rate\n");
+ return;
+ }
+ per_pipe_info->vsync_ft_usec =
+ (mode->htotal * mode->vtotal * 1000) / mode->clock;
+ cur_params->active_pipes_bitmask |= (1 << intel_crtc->pipe);
+ cur_params->vbi_sync_on_pipes |= (1 << intel_crtc->pipe);
+ }
+
+ if (old_params.per_pipe_info[intel_crtc->pipe].data != per_pipe_info->data)
+ notify = true;
+ }
+
+ cur_params->num_active_pipes = hweight32(cur_params->active_pipes_bitmask);
+
+ /* Compare old display mode with current mode. Notify SLPC if it is changed. */
+ if (cur_params->global_data != old_params.global_data)
+ notify = true;
+
+ if (notify) {
+ host2guc_slpc_display_mode_change(dev);
+ }
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index b963fe7..d560d86 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -149,5 +149,8 @@ void intel_slpc_suspend(struct drm_device *dev);
void intel_slpc_disable(struct drm_device *dev);
void intel_slpc_enable(struct drm_device *dev);
void intel_slpc_reset(struct drm_device *dev);
+void intel_slpc_update_display_mode_info(struct drm_device *dev);
+void intel_slpc_update_atomic_commit_info(struct drm_device *dev,
+ struct drm_atomic_state *state);
#endif
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 15/26] drm/i915/slpc: Notification of Refresh Rate change
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (13 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 14/26] drm/i915/slpc: Notification of Display mode change tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 16/26] drm/i915/slpc: Add slpc_status enum values tom.orourke
` (11 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Sagar Arun Kamble <sagar.a.kamble@intel.com>
This patch will inform GuC SLPC about changes in the refresh rate
due to Seamless DRRS. Refresh rate changes due to Static DRRS will
be notified via commit path.
v2: Rebased on previous changed patch and printed error message if
H2G action fails.
v2(torourke): Updates suggested by Paulo: replace HAS_SLPC with
intel_slpc_active. return void instead of ignored error code.
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 2 ++
drivers/gpu/drm/i915/intel_slpc.c | 23 +++++++++++++++++++++++
drivers/gpu/drm/i915/intel_slpc.h | 1 +
3 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 351a8f3..98e1974 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5433,6 +5433,8 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
dev_priv->drrs.refresh_rate_type = index;
DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
+
+ intel_slpc_update_display_rr_info(dev, refresh_rate);
}
/**
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 58f90b3..524ad63 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -332,3 +332,26 @@ void intel_slpc_update_atomic_commit_info(struct drm_device *dev,
host2guc_slpc_display_mode_change(dev);
}
}
+
+void intel_slpc_update_display_rr_info(struct drm_device *dev, u32 refresh_rate)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_crtc *crtc;
+ struct intel_display_pipe_info *per_pipe_info;
+ struct intel_slpc_display_mode_event_params *display_params;
+
+ if (!intel_slpc_active(dev))
+ return;
+
+ if (!refresh_rate)
+ return;
+
+ display_params = &dev_priv->guc.slpc.display_mode_params;
+ crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
+
+ per_pipe_info = &display_params->per_pipe_info[to_intel_crtc(crtc)->pipe];
+ per_pipe_info->refresh_rate = refresh_rate;
+ per_pipe_info->vsync_ft_usec = 1000000 / refresh_rate;
+
+ host2guc_slpc_display_mode_change(dev);
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index d560d86..06f1b28 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -152,5 +152,6 @@ void intel_slpc_reset(struct drm_device *dev);
void intel_slpc_update_display_mode_info(struct drm_device *dev);
void intel_slpc_update_atomic_commit_info(struct drm_device *dev,
struct drm_atomic_state *state);
+void intel_slpc_update_display_rr_info(struct drm_device *dev, u32 refresh_rate);
#endif
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 16/26] drm/i915/slpc: Add slpc_status enum values
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (14 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 15/26] drm/i915/slpc: Notification of Refresh Rate change tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 17/26] drm/i915/slpc: Add parameter unset/set/get functions tom.orourke
` (10 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/intel_slpc.h | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 06f1b28..de2df0c 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -28,6 +28,33 @@
#define SLPC_MINOR_VER 4
#define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
+enum slpc_status {
+ SLPC_STATUS_OK = 0,
+ SLPC_STATUS_ERROR = 1,
+ SLPC_STATUS_ILLEGAL_COMMAND = 2,
+ SLPC_STATUS_INVALID_ARGS = 3,
+ SLPC_STATUS_INVALID_PARAMS = 4,
+ SLPC_STATUS_INVALID_DATA = 5,
+ SLPC_STATUS_OUT_OF_RANGE = 6,
+ SLPC_STATUS_NOT_SUPPORTED = 7,
+ SLPC_STATUS_NOT_IMPLEMENTED = 8,
+ SLPC_STATUS_NO_DATA = 9,
+ SLPC_STATUS_EVENT_NOT_REGISTERED = 10,
+ SLPC_STATUS_REGISTER_LOCKED = 11,
+ SLPC_STATUS_TEMPORARILY_UNAVAILABLE = 12,
+ SLPC_STATUS_VALUE_ALREADY_SET = 13,
+ SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
+ SLPC_STATUS_VALUE_NOT_CHANGED = 15,
+ SLPC_STATUS_MISMATCHING_VERSION = 16,
+ SLPC_STATUS_MEMIO_ERROR = 17,
+ SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 18,
+ SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 19,
+ SLPC_STATUS_NO_EVENT_QUEUED = 20,
+ SLPC_STATUS_OUT_OF_SPACE = 21,
+ SLPC_STATUS_TIMEOUT = 22,
+ SLPC_STATUS_NO_LOCK =23,
+};
+
enum slpc_event_id {
SLPC_EVENT_RESET = 0,
SLPC_EVENT_SHUTDOWN = 1,
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 17/26] drm/i915/slpc: Add parameter unset/set/get functions
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (15 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 16/26] drm/i915/slpc: Add slpc_status enum values tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 18/26] drm/i915/slpc: Add slpc support for max/min freq tom.orourke
` (9 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Tom O'Rourke <Tom.O'Rourke@intel.com>
Add slpc_param_id enum values.
Add events for setting/unsetting parameters.
v2: use host2guc_slpc
update slcp_param_id enum values for SLPC 2015.2.4
return void instead of ignored error code (Paulo)
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/intel_slpc.c | 104 ++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_slpc.h | 26 +++++++++-
2 files changed, 129 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 524ad63..e7f49db 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -88,6 +88,33 @@ static void host2guc_slpc_display_mode_change(struct drm_device *dev)
host2guc_slpc(dev_priv, data, 7);
}
+static void host2guc_slpc_set_param(struct drm_device *dev,
+ enum slpc_param_id id, u32 value)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 data[4];
+
+ data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+ data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2);
+ data[2] = (u32) id;
+ data[3] = value;
+
+ host2guc_slpc(dev_priv, data, 4);
+}
+
+static void host2guc_slpc_unset_param(struct drm_device *dev,
+ enum slpc_param_id id)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 data[3];
+
+ data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+ data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1);
+ data[2] = (u32) id;
+
+ host2guc_slpc(dev_priv, data, 3);
+}
+
static u8 slpc_get_platform_sku(struct drm_i915_gem_object *obj)
{
struct drm_device *dev = obj->base.dev;
@@ -355,3 +382,80 @@ void intel_slpc_update_display_rr_info(struct drm_device *dev, u32 refresh_rate)
host2guc_slpc_display_mode_change(dev);
}
+
+void intel_slpc_unset_param(struct drm_device *dev, enum slpc_param_id id)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_gem_object *obj;
+ struct page *page;
+ struct slpc_shared_data *data = NULL;
+
+ obj = dev_priv->guc.slpc.shared_data_obj;
+ if (obj) {
+ page = i915_gem_object_get_page(obj, 0);
+ if (page)
+ data = kmap_atomic(page);
+ }
+
+ if (data) {
+ data->override_parameters_set_bits[id >> 5]
+ &= (~(1 << (id % 32)));
+ data->override_parameters_values[id] = 0;
+ kunmap_atomic(data);
+
+ host2guc_slpc_unset_param(dev, id);
+ }
+}
+
+void intel_slpc_set_param(struct drm_device *dev, enum slpc_param_id id,
+ u32 value)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_gem_object *obj;
+ struct page *page;
+ struct slpc_shared_data *data = NULL;
+
+ obj = dev_priv->guc.slpc.shared_data_obj;
+ if (obj) {
+ page = i915_gem_object_get_page(obj, 0);
+ if (page)
+ data = kmap_atomic(page);
+ }
+
+ if (data) {
+ data->override_parameters_set_bits[id >> 5]
+ |= (1 << (id % 32));
+ data->override_parameters_values[id] = value;
+ kunmap_atomic(data);
+
+ host2guc_slpc_set_param(dev, id, value);
+ }
+}
+
+void intel_slpc_get_param(struct drm_device *dev, enum slpc_param_id id,
+ int *overriding, u32 *value)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_gem_object *obj;
+ struct page *page;
+ struct slpc_shared_data *data = NULL;
+ u32 bits;
+
+ obj = dev_priv->guc.slpc.shared_data_obj;
+ if (obj) {
+ page = i915_gem_object_get_page(obj, 0);
+ if (page)
+ data = kmap_atomic(page);
+ }
+
+ if (data) {
+ if (overriding) {
+ bits = data->override_parameters_set_bits[id >> 5];
+ *overriding = (0 != (bits & (1 << (id % 32))));
+ }
+ if (value)
+ *value = data->override_parameters_values[id];
+
+ kunmap_atomic(data);
+ }
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index de2df0c..b7ad440 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -69,6 +69,26 @@ enum slpc_event_id {
#define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
#define SLPC_EVENT_STATUS_MASK 0xFF
+enum slpc_param_id {
+ SLPC_PARAM_TASK_ENABLE_GTPERF = 0,
+ SLPC_PARAM_TASK_DISABLE_GTPERF = 1,
+ SLPC_PARAM_TASK_ENABLE_BALANCER = 2,
+ SLPC_PARAM_TASK_DISABLE_BALANCER = 3,
+ SLPC_PARAM_TASK_ENABLE_DCC = 4,
+ SLPC_PARAM_TASK_DISABLE_DCC = 5,
+ SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,
+ SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
+ SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
+ SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,
+ SLPC_PARAM_DFPS_THRESHOLD_MAX_FPS = 10,
+ SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
+ SLPC_PARAM_DFPS_DISABLE_FRAMERATE_STALLING = 12,
+ SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
+ SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
+ SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
+ SLPC_PARAM_GLOBAL_DISABE_IA_GT_BALANCING = 16,
+};
+
enum slpc_global_state {
SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
SLPC_GLOBAL_STATE_INITIALIZING = 1,
@@ -180,5 +200,9 @@ void intel_slpc_update_display_mode_info(struct drm_device *dev);
void intel_slpc_update_atomic_commit_info(struct drm_device *dev,
struct drm_atomic_state *state);
void intel_slpc_update_display_rr_info(struct drm_device *dev, u32 refresh_rate);
-
+void intel_slpc_unset_param(struct drm_device *dev, enum slpc_param_id id);
+void intel_slpc_set_param(struct drm_device *dev, enum slpc_param_id id,
+ u32 value);
+void intel_slpc_get_param(struct drm_device *dev, enum slpc_param_id id,
+ int *overriding, u32 *value);
#endif
--
1.9.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 18/26] drm/i915/slpc: Add slpc support for max/min freq
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (16 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 17/26] drm/i915/slpc: Add parameter unset/set/get functions tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 19/26] drm/i915/slpc: Add enable/disable debugfs for slpc tom.orourke
` (8 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Tom O'Rourke <Tom.O'Rourke@intel.com>
Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.
v2: Update for SLPC 2015.2.4 (params for both slice and unslice)
Replace HAS_SLPC with intel_slpc_active() (Paulo)
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 16 ++++++++++++++++
drivers/gpu/drm/i915/i915_sysfs.c | 18 ++++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 6bf9282..0cc0e70 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4960,6 +4960,14 @@ i915_max_freq_set(void *data, u64 val)
}
dev_priv->rps.max_freq_softlimit = val;
+ if (intel_slpc_active(dev)) {
+ intel_slpc_set_param(dev,
+ SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(dev,
+ SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ }
intel_set_rps(dev, val);
@@ -5027,6 +5035,14 @@ i915_min_freq_set(void *data, u64 val)
}
dev_priv->rps.min_freq_softlimit = val;
+ if (intel_slpc_active(dev)) {
+ intel_slpc_set_param(dev,
+ SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(dev,
+ SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ }
intel_set_rps(dev, val);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 923a63a..7b8e73e 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -392,6 +392,15 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
dev_priv->rps.max_freq_softlimit = val;
+ if (intel_slpc_active(dev)) {
+ intel_slpc_set_param(dev,
+ SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(dev,
+ SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ }
+
val = clamp_t(int, dev_priv->rps.cur_freq,
dev_priv->rps.min_freq_softlimit,
dev_priv->rps.max_freq_softlimit);
@@ -456,6 +465,15 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
dev_priv->rps.min_freq_softlimit = val;
+ if (intel_slpc_active(dev)) {
+ intel_slpc_set_param(dev,
+ SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(dev,
+ SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ }
+
val = clamp_t(int, dev_priv->rps.cur_freq,
dev_priv->rps.min_freq_softlimit,
dev_priv->rps.max_freq_softlimit);
--
1.9.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 19/26] drm/i915/slpc: Add enable/disable debugfs for slpc
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (17 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 18/26] drm/i915/slpc: Add slpc support for max/min freq tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 20/26] drm/i915/slpc: Add broxton support tom.orourke
` (7 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Tom O'Rourke <Tom.O'Rourke@intel.com>
Adds debugfs hooks for each slpc task.
The enable/disable debugfs files are
i915_slpc_gtperf, i915_slpc_balancer, and i915_slpc_dcc.
Each of these can take the values:
"default", "enabled", or "disabled"
v2: update for SLPC v2015.2.4
dfps and turbo merged and renamed "gtperf"
ibc split out and renamed "balancer"
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 250 ++++++++++++++++++++++++++++++++++++
1 file changed, 250 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 0cc0e70..54e40f1 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1124,6 +1124,253 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
i915_next_seqno_get, i915_next_seqno_set,
"0x%llx\n");
+static int slpc_enable_disable_get(struct drm_device *dev, u64 *val,
+ enum slpc_param_id enable_id,
+ enum slpc_param_id disable_id)
+{
+ int override_enable, override_disable;
+ u32 value_enable, value_disable;
+ int ret = 0;
+
+ if (!intel_slpc_active(dev)) {
+ ret = -ENODEV;
+ } else if (val) {
+ intel_slpc_get_param(dev, enable_id, &override_enable,
+ &value_enable);
+ intel_slpc_get_param(dev, disable_id, &override_disable,
+ &value_disable);
+
+ /* set the output value:
+ * 0: default
+ * 1: enabled
+ * 2: disabled
+ * 3: unknown (should not happen)
+ */
+ if (override_disable && (1 == value_disable))
+ *val = 2;
+ else if (override_enable && (1 == value_enable))
+ *val = 1;
+ else if (!override_enable && !override_disable)
+ *val = 0;
+ else
+ *val = 3;
+
+ } else {
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+static int slpc_enable_disable_set(struct drm_device *dev, u64 val,
+ enum slpc_param_id enable_id,
+ enum slpc_param_id disable_id)
+{
+ int ret = 0;
+
+ if (!intel_slpc_active(dev)) {
+ ret = -ENODEV;
+ } else if (0 == val) {
+ /* set default */
+ intel_slpc_unset_param(dev, enable_id);
+ intel_slpc_unset_param(dev, disable_id);
+ } else if (1 == val) {
+ /* set enable */
+ intel_slpc_set_param(dev, enable_id, 1);
+ intel_slpc_unset_param(dev, disable_id);
+ } else if (2 == val) {
+ /* set disable */
+ intel_slpc_set_param(dev, disable_id, 1);
+ intel_slpc_unset_param(dev, enable_id);
+ } else {
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+static void slpc_param_show(struct seq_file *m, enum slpc_param_id enable_id,
+ enum slpc_param_id disable_id)
+{
+ struct drm_device *dev = m->private;
+ const char *status;
+ u64 val;
+ int ret;
+
+ ret = slpc_enable_disable_get(dev, &val, enable_id, disable_id);
+
+ if (ret) {
+ seq_printf(m, "error %d\n", ret);
+ } else {
+ switch (val) {
+ case 0:
+ status = "default\n";
+ break;
+
+ case 1:
+ status = "enabled\n";
+ break;
+
+ case 2:
+ status = "disabled\n";
+ break;
+
+ default:
+ status = "unknown\n";
+ break;
+ }
+
+ seq_puts(m, status);
+ }
+}
+
+static int slpc_param_write(struct seq_file *m, const char __user *ubuf,
+ size_t len, enum slpc_param_id enable_id,
+ enum slpc_param_id disable_id)
+{
+ struct drm_device *dev = m->private;
+ u64 val;
+ int ret = 0;
+ char buf[10];
+
+ if (len >= sizeof(buf))
+ ret = -EINVAL;
+ else if (copy_from_user(buf, ubuf, len))
+ ret = -EFAULT;
+ else
+ buf[len] = '\0';
+
+ if (!ret) {
+ if (!strncmp(buf, "default", 7))
+ val = 0;
+ else if (!strncmp(buf, "enabled", 7))
+ val = 1;
+ else if (!strncmp(buf, "disabled", 8))
+ val = 2;
+ else
+ ret = -EINVAL;
+ }
+
+ if (!ret)
+ ret = slpc_enable_disable_set(dev, val, enable_id, disable_id);
+
+ return ret;
+}
+
+static int slpc_gtperf_show(struct seq_file *m, void *data)
+{
+ slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_GTPERF,
+ SLPC_PARAM_TASK_DISABLE_GTPERF);
+
+ return 0;
+}
+
+static int slpc_gtperf_open(struct inode *inode, struct file *file)
+{
+ struct drm_connector *dev = inode->i_private;
+
+ return single_open(file, slpc_gtperf_show, dev);
+}
+
+static ssize_t slpc_gtperf_write(struct file *file, const char __user *ubuf,
+ size_t len, loff_t *offp)
+{
+ struct seq_file *m = file->private_data;
+ int ret = 0;
+
+ ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_GTPERF,
+ SLPC_PARAM_TASK_DISABLE_GTPERF);
+ if (ret)
+ return (size_t) ret;
+
+ return len;
+}
+
+static const struct file_operations i915_slpc_gtperf_fops = {
+ .owner = THIS_MODULE,
+ .open = slpc_gtperf_open,
+ .release = single_release,
+ .read = seq_read,
+ .write = slpc_gtperf_write,
+ .llseek = seq_lseek
+};
+
+static int slpc_balancer_show(struct seq_file *m, void *data)
+{
+ slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_BALANCER,
+ SLPC_PARAM_TASK_DISABLE_BALANCER);
+
+ return 0;
+}
+
+static int slpc_balancer_open(struct inode *inode, struct file *file)
+{
+ struct drm_connector *dev = inode->i_private;
+
+ return single_open(file, slpc_balancer_show, dev);
+}
+
+static ssize_t slpc_balancer_write(struct file *file, const char __user *ubuf,
+ size_t len, loff_t *offp)
+{
+ struct seq_file *m = file->private_data;
+ int ret = 0;
+
+ ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_BALANCER,
+ SLPC_PARAM_TASK_DISABLE_BALANCER);
+ if (ret)
+ return (size_t) ret;
+
+ return len;
+}
+
+static const struct file_operations i915_slpc_balancer_fops = {
+ .owner = THIS_MODULE,
+ .open = slpc_balancer_open,
+ .release = single_release,
+ .read = seq_read,
+ .write = slpc_balancer_write,
+ .llseek = seq_lseek
+};
+
+static int slpc_dcc_show(struct seq_file *m, void *data)
+{
+ slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_DCC,
+ SLPC_PARAM_TASK_DISABLE_DCC);
+
+ return 0;
+}
+
+static int slpc_dcc_open(struct inode *inode, struct file *file)
+{
+ struct drm_connector *dev = inode->i_private;
+
+ return single_open(file, slpc_dcc_show, dev);
+}
+
+static ssize_t slpc_dcc_write(struct file *file, const char __user *ubuf,
+ size_t len, loff_t *offp)
+{
+ struct seq_file *m = file->private_data;
+ int ret = 0;
+
+ ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_DCC,
+ SLPC_PARAM_TASK_DISABLE_DCC);
+ if (ret)
+ return (size_t) ret;
+
+ return len;
+}
+
+static const struct file_operations i915_slpc_dcc_fops = {
+ .owner = THIS_MODULE,
+ .open = slpc_dcc_open,
+ .release = single_release,
+ .read = seq_read,
+ .write = slpc_dcc_write,
+ .llseek = seq_lseek
+};
+
static int i915_frequency_info(struct seq_file *m, void *unused)
{
struct drm_info_node *node = m->private;
@@ -5421,6 +5668,9 @@ static const struct i915_debugfs_files {
const struct file_operations *fops;
} i915_debugfs_files[] = {
{"i915_wedged", &i915_wedged_fops},
+ {"i915_slpc_gtperf", &i915_slpc_gtperf_fops},
+ {"i915_slpc_balancer", &i915_slpc_balancer_fops},
+ {"i915_slpc_dcc", &i915_slpc_dcc_fops},
{"i915_max_freq", &i915_max_freq_fops},
{"i915_min_freq", &i915_min_freq_fops},
{"i915_cache_sharing", &i915_cache_sharing_fops},
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 20/26] drm/i915/slpc: Add broxton support
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (18 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 19/26] drm/i915/slpc: Add enable/disable debugfs for slpc tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 21/26] drm/i915/slpc: Add i915_slpc_info to debugfs tom.orourke
` (6 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Tom O'Rourke <Tom.O'Rourke@intel.com>
Adds has_slpc to broxton info and adds broxton to
version check. The SLPC interface version 2015.2.4
is found in Broxton Guc v5.
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/intel_guc_loader.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a23d673..7c00246 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -344,6 +344,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_ddi = 1,
.has_fpga_dbg = 1,
.has_fbc = 1,
+ .has_slpc = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
};
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index a3848bf..aa6eca9 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -136,7 +136,8 @@ static void slpc_version_check(struct drm_device *dev, struct intel_guc_fw *guc_
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_device_info *info;
- if (IS_SKYLAKE(dev) && (guc_fw->guc_fw_major_found != 6)) {
+ if ((IS_SKYLAKE(dev) && (guc_fw->guc_fw_major_found != 6))
+ || (IS_BROXTON(dev) && (guc_fw->guc_fw_major_found != 5))) {
info = (struct intel_device_info *) &dev_priv->info;
info->has_slpc = 0;
}
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 21/26] drm/i915/slpc: Add i915_slpc_info to debugfs
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (19 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 20/26] drm/i915/slpc: Add broxton support tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 22/26] DO NOT MERGE: drm/i915: Change SKL guc version wanted to 6.0 tom.orourke
` (5 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Tom O'Rourke <Tom.O'Rourke@intel.com>
i915_slpc_info shows the contents of SLPC shared data
parsed into text format.
v2: reformat slpc info (Radek)
squashed query task state info
in slpc info, kunmap before seq_print (Paulo)
return void instead of ignored return value (Paulo)
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 184 ++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_slpc.c | 23 +++++
drivers/gpu/drm/i915/intel_slpc.h | 1 +
3 files changed, 208 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 54e40f1..806b095 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1371,6 +1371,189 @@ static const struct file_operations i915_slpc_dcc_fops = {
.llseek = seq_lseek
};
+static int i915_slpc_info(struct seq_file *m, void *unused)
+{
+ struct drm_info_node *node = m->private;
+ struct drm_device *dev = node->minor->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_gem_object *obj;
+ struct page *page;
+ void *pv = NULL;
+ struct slpc_shared_data data;
+ int i, value;
+ enum slpc_global_state global_state;
+ enum slpc_platform_sku platform_sku;
+ enum slpc_host_os host_os;
+ enum slpc_power_plan power_plan;
+ enum slpc_power_source power_source;
+
+ obj = dev_priv->guc.slpc.shared_data_obj;
+ if (obj) {
+ intel_slpc_query_task_state(dev);
+
+ page = i915_gem_object_get_page(obj, 0);
+ if (page)
+ pv = kmap_atomic(page);
+ }
+
+ if (pv) {
+ data = *(struct slpc_shared_data *) pv;
+ kunmap_atomic(pv);
+
+ seq_printf(m, "SLPC Version: %d.%d.%d (0x%8x)\n",
+ data.slpc_version >> 16,
+ (data.slpc_version >> 8) & 0xFF,
+ data.slpc_version & 0xFF,
+ data.slpc_version);
+ seq_printf(m, "shared data size: %d\n", data.shared_data_size);
+
+ seq_printf(m, "global state: %d (", data.global_state);
+ global_state = (enum slpc_global_state) data.global_state;
+ switch (global_state) {
+ case SLPC_GLOBAL_STATE_NOT_RUNNING:
+ seq_puts(m, "not running)\n");
+ break;
+ case SLPC_GLOBAL_STATE_INITIALIZING:
+ seq_puts(m, "initializing)\n");
+ break;
+ case SLPC_GLOBAL_STATE_RESETING:
+ seq_puts(m, "resetting)\n");
+ break;
+ case SLPC_GLOBAL_STATE_RUNNING:
+ seq_puts(m, "running)\n");
+ break;
+ case SLPC_GLOBAL_STATE_SHUTTING_DOWN:
+ seq_puts(m, "shutting down)\n");
+ break;
+ case SLPC_GLOBAL_STATE_ERROR:
+ seq_puts(m, "error)\n");
+ break;
+ default:
+ seq_puts(m, "unknown)\n");
+ break;
+ }
+
+ seq_printf(m, "sku: %d (", data.platform_info.platform_sku);
+ platform_sku = (enum slpc_platform_sku)
+ data.platform_info.platform_sku;
+ switch (platform_sku) {
+ case SLPC_PLATFORM_SKU_UNDEFINED:
+ seq_puts(m, "undefined)\n");
+ break;
+ case SLPC_PLATFORM_SKU_ULX:
+ seq_puts(m, "ULX)\n");
+ break;
+ case SLPC_PLATFORM_SKU_ULT:
+ seq_puts(m, "ULT)\n");
+ break;
+ case SLPC_PLATFORM_SKU_T:
+ seq_puts(m, "T)\n");
+ break;
+ case SLPC_PLATFORM_SKU_MOBL:
+ seq_puts(m, "Mobile)\n");
+ break;
+ case SLPC_PLATFORM_SKU_DT:
+ seq_puts(m, "DT)\n");
+ break;
+ case SLPC_PLATFORM_SKU_UNKNOWN:
+ default:
+ seq_puts(m, "unknown)\n");
+ break;
+ }
+ seq_printf(m, "slice count: %d\n",
+ data.platform_info.slice_count);
+
+ seq_printf(m, "host OS: %d (", data.platform_info.host_os);
+ host_os = (enum slpc_host_os) data.platform_info.host_os;
+ switch (host_os) {
+ case SLPC_HOST_OS_UNDEFINED:
+ seq_puts(m, "undefined)\n");
+ break;
+ case SLPC_HOST_OS_WINDOWS_8:
+ seq_puts(m, "Windows 8)\n");
+ break;
+ default:
+ seq_puts(m, "unknown)\n");
+ break;
+ }
+
+ seq_printf(m, "power plan/source: 0x%x\n\tplan:\t",
+ data.platform_info.power_plan_source);
+ power_plan = (enum slpc_power_plan)
+ data.platform_info.power_plan_source & 0x3F;
+ power_source = (enum slpc_power_source)
+ data.platform_info.power_plan_source >> 6;
+ switch (power_plan) {
+ case SLPC_POWER_PLAN_UNDEFINED:
+ seq_puts(m, "undefined");
+ break;
+ case SLPC_POWER_PLAN_BATTERY_SAVER:
+ seq_puts(m, "battery saver");
+ break;
+ case SLPC_POWER_PLAN_BALANCED:
+ seq_puts(m, "balanced");
+ break;
+ case SLPC_POWER_PLAN_PERFORMANCE:
+ seq_puts(m, "performance");
+ break;
+ case SLPC_POWER_PLAN_UNKNOWN:
+ default:
+ seq_puts(m, "unknown");
+ break;
+ }
+ seq_puts(m, "\n\tsource:\t");
+ switch (power_source) {
+ case SLPC_POWER_SOURCE_UNDEFINED:
+ seq_puts(m, "undefined\n");
+ break;
+ case SLPC_POWER_SOURCE_AC:
+ seq_puts(m, "AC\n");
+ break;
+ case SLPC_POWER_SOURCE_DC:
+ seq_puts(m, "DC\n");
+ break;
+ case SLPC_POWER_SOURCE_UNKNOWN:
+ default:
+ seq_puts(m, "unknown\n");
+ break;
+ }
+
+ seq_printf(m, "IA frequency (MHz):\n\tP0: %d\n\tP1: %d\n\tPe: %d\n\tPn: %d\n",
+ data.platform_info.P0_freq * 50,
+ data.platform_info.P1_freq * 50,
+ data.platform_info.Pe_freq * 50,
+ data.platform_info.Pn_freq * 50);
+ seq_printf(m, "RAPL package power limits:\n\t0x%08x\n\t0x%08x\n",
+ data.platform_info.package_rapl_limit_high,
+ data.platform_info.package_rapl_limit_low);
+ seq_printf(m, "task state data: 0x%08x\n",
+ data.task_state_data);
+ seq_printf(m, "\tturbo active: %d\n",
+ (data.task_state_data & 1));
+ seq_printf(m, "\tdfps stall possible: %d\n\tgame mode: %d\n\tdfps target fps: %d\n",
+ (data.task_state_data & 2),
+ (data.task_state_data & 4),
+ (data.task_state_data >> 3) & 0xFF);
+
+ seq_puts(m, "override parameter bitfield\n");
+ for (i=0; i < SLPC_OVERRIDE_BITFIELD_SIZE; i++)
+ seq_printf(m, "%d: 0x%08x\n", i,
+ data.override_parameters_set_bits[i]);
+
+ seq_puts(m, "override parameters (only non-zero shown)\n");
+ for (i=0; i < SLPC_MAX_OVERRIDE_PARAMETERS; i++) {
+ value = data.override_parameters_values[i];
+ if (value)
+ seq_printf(m, "%d: 0x%8x\n", i, value);
+ }
+
+ } else {
+ seq_puts(m, "no SLPC info available\n");
+ }
+
+ return 0;
+}
+
static int i915_frequency_info(struct seq_file *m, void *unused)
{
struct drm_info_node *node = m->private;
@@ -5626,6 +5809,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_guc_info", i915_guc_info, 0},
{"i915_guc_load_status", i915_guc_load_status_info, 0},
{"i915_guc_log_dump", i915_guc_log_dump, 0},
+ {"i915_slpc_info", i915_slpc_info, 0},
{"i915_frequency_info", i915_frequency_info, 0},
{"i915_hangcheck_info", i915_hangcheck_info, 0},
{"i915_drpc_info", i915_drpc_info, 0},
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index e7f49db..7fe6e87 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -115,6 +115,23 @@ static void host2guc_slpc_unset_param(struct drm_device *dev,
host2guc_slpc(dev_priv, data, 3);
}
+static void host2guc_slpc_query_task_state(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_gem_object *obj = dev_priv->guc.slpc.shared_data_obj;
+ u32 data[4];
+ u64 shared_data_gtt_offset = i915_gem_obj_ggtt_offset(obj);
+
+ data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+ data[1] = SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2);
+ data[2] = lower_32_bits(shared_data_gtt_offset);
+ data[3] = upper_32_bits(shared_data_gtt_offset);
+
+ WARN_ON(0 != data[3]);
+
+ host2guc_slpc(dev_priv, data, 4);
+}
+
static u8 slpc_get_platform_sku(struct drm_i915_gem_object *obj)
{
struct drm_device *dev = obj->base.dev;
@@ -459,3 +476,9 @@ void intel_slpc_get_param(struct drm_device *dev, enum slpc_param_id id,
kunmap_atomic(data);
}
}
+
+void intel_slpc_query_task_state(struct drm_device *dev)
+{
+ if (intel_slpc_active(dev))
+ host2guc_slpc_query_task_state(dev);
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index b7ad440..338c6c6 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -205,4 +205,5 @@ void intel_slpc_set_param(struct drm_device *dev, enum slpc_param_id id,
u32 value);
void intel_slpc_get_param(struct drm_device *dev, enum slpc_param_id id,
int *overriding, u32 *value);
+void intel_slpc_query_task_state(struct drm_device *dev);
#endif
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 22/26] DO NOT MERGE: drm/i915: Change SKL guc version wanted to 6.0
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (20 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 21/26] drm/i915/slpc: Add i915_slpc_info to debugfs tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 23/26] DO NOT MERGE: drm/i915/bxt: Add Broxton to guc loader tom.orourke
` (4 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Tom O'Rourke <Tom.O'Rourke@intel.com>
Do not merge until SKL guc ver6 is published.
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/intel_guc_loader.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index aa6eca9..569cba3 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -59,7 +59,7 @@
*
*/
-#define I915_SKL_GUC_UCODE "i915/skl_guc_ver4.bin"
+#define I915_SKL_GUC_UCODE "i915/skl_guc_ver6.bin"
MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
/* User-friendly representation of an enum */
@@ -629,8 +629,8 @@ void intel_guc_ucode_init(struct drm_device *dev)
fw_path = NULL;
} else if (IS_SKYLAKE(dev)) {
fw_path = I915_SKL_GUC_UCODE;
- guc_fw->guc_fw_major_wanted = 4;
- guc_fw->guc_fw_minor_wanted = 3;
+ guc_fw->guc_fw_major_wanted = 6;
+ guc_fw->guc_fw_minor_wanted = 0;
} else {
i915.enable_guc_submission = false;
fw_path = ""; /* unknown device */
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 23/26] DO NOT MERGE: drm/i915/bxt: Add Broxton to guc loader
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (21 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 22/26] DO NOT MERGE: drm/i915: Change SKL guc version wanted to 6.0 tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 24/26] DO NOT MERGE: drm/i915: resize the GuC WOPCM for rc6 tom.orourke
` (3 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Tom O'Rourke <Tom.O'Rourke@intel.com>
This patch is expected as part of another series
and is included for convenience in testing this
series.
Do not merge unless Broxton guc v5 firmware is available.
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 569cba3..b88e7ea 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -62,6 +62,9 @@
#define I915_SKL_GUC_UCODE "i915/skl_guc_ver6.bin"
MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
+#define I915_BXT_GUC_UCODE "i915/bxt_guc_ver5.bin"
+MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
+
/* User-friendly representation of an enum */
const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
{
@@ -631,6 +634,10 @@ void intel_guc_ucode_init(struct drm_device *dev)
fw_path = I915_SKL_GUC_UCODE;
guc_fw->guc_fw_major_wanted = 6;
guc_fw->guc_fw_minor_wanted = 0;
+ } else if (IS_BROXTON(dev)) {
+ fw_path = I915_BXT_GUC_UCODE;
+ guc_fw->guc_fw_major_wanted = 5;
+ guc_fw->guc_fw_minor_wanted = 0;
} else {
i915.enable_guc_submission = false;
fw_path = ""; /* unknown device */
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 24/26] DO NOT MERGE: drm/i915: resize the GuC WOPCM for rc6
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (22 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 23/26] DO NOT MERGE: drm/i915/bxt: Add Broxton to guc loader tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 25/26] DO NOT MERGE: drm/i915: Enable GuC submission, where supported tom.orourke
` (2 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni
From: Peter Antoine <peter.antoine@intel.com>
This patch resizes the GuC WOPCM to so that the GuC and the RC6 memory
spaces do not overlap.
DO NOT MERGE: This patch is expected as part of another
series and is included for convenience in testing this
series.
Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
Acked-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/i915_guc_reg.h | 3 ++-
drivers/gpu/drm/i915/intel_guc_loader.c | 6 +++++-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
index e4ba582..e1f0f47 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -59,7 +59,8 @@
#define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
#define GUC_WOPCM_SIZE _MMIO(0xc050)
-#define GUC_WOPCM_SIZE_VALUE (0x80 << 12) /* 512KB */
+#define GUC_WOPCM_SIZE_VALUE (0x80 << 12) /* 512KB */
+#define BXT_GUC_WOPCM_SIZE_VALUE (0x70 << 12) /* 448KB */
/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
#define GUC_WOPCM_TOP (GUC_WOPCM_SIZE_VALUE)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index b88e7ea..d269e79 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -343,7 +343,11 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
/* init WOPCM */
- I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
+ if (IS_BROXTON(dev))
+ I915_WRITE(GUC_WOPCM_SIZE, BXT_GUC_WOPCM_SIZE_VALUE);
+ else
+ I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
+
I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
/* Enable MIA caching. GuC clock gating is disabled. */
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 25/26] DO NOT MERGE: drm/i915: Enable GuC submission, where supported
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (23 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 24/26] DO NOT MERGE: drm/i915: resize the GuC WOPCM for rc6 tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 0:34 ` [PATCH 26/26] DO NOT MERGE: drm/i915: Enable SLPC, " tom.orourke
2016-03-09 8:03 ` ✗ Fi.CI.BAT: failure for Add support for GuC-based SLPC (rev2) Patchwork
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni
From: Dave Gordon <david.s.gordon@intel.com>
DO NOT MERGE: This patch is added for convenience in
reviewing SLPC patch series. This patch should be
merged as part of a separate series to enable guc
submission by default.
v5:
Rebased
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Acked-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/i915_params.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 1cee0ea..daae5e7 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -55,7 +55,7 @@ struct i915_params i915 __read_mostly = {
.verbose_state_checks = 1,
.nuclear_pageflip = 0,
.edp_vswing = 0,
- .enable_guc_submission = false,
+ .enable_guc_submission = true,
.guc_log_level = -1,
};
@@ -202,7 +202,7 @@ MODULE_PARM_DESC(edp_vswing,
"2=default swing(400mV))");
module_param_named_unsafe(enable_guc_submission, i915.enable_guc_submission, bool, 0400);
-MODULE_PARM_DESC(enable_guc_submission, "Enable GuC submission (default:false)");
+MODULE_PARM_DESC(enable_guc_submission, "Enable GuC submission (default:true)");
module_param_named(guc_log_level, i915.guc_log_level, int, 0400);
MODULE_PARM_DESC(guc_log_level,
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 26/26] DO NOT MERGE: drm/i915: Enable SLPC, where supported
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (24 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 25/26] DO NOT MERGE: drm/i915: Enable GuC submission, where supported tom.orourke
@ 2016-03-09 0:34 ` tom.orourke
2016-03-09 8:03 ` ✗ Fi.CI.BAT: failure for Add support for GuC-based SLPC (rev2) Patchwork
26 siblings, 0 replies; 28+ messages in thread
From: tom.orourke @ 2016-03-09 0:34 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni, Tom O'Rourke
From: Tom O'Rourke <Tom.O'Rourke@intel.com>
This patch makes SLPC enabled by default on
platforms with hardware/firmware support.
DO NOT MERGE: This patch is added for convenience in
reviewing SLPC patch series. This patch should be
merged after validation results show benefits of using SLPC.
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/i915_params.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index daae5e7..a5b8fff 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -36,7 +36,7 @@ struct i915_params i915 __read_mostly = {
.enable_dc = -1,
.enable_fbc = -1,
.enable_execlists = -1,
- .enable_slpc = 0,
+ .enable_slpc = -1,
.enable_hangcheck = true,
.enable_ppgtt = -1,
.enable_psr = -1,
@@ -129,7 +129,7 @@ MODULE_PARM_DESC(enable_execlists,
module_param_named_unsafe(enable_slpc, i915.enable_slpc, int, 0400);
MODULE_PARM_DESC(enable_slpc,
"Override single-loop-power-controller (slpc) usage. "
- "(-1=auto, 0=disabled [default], 1=enabled)");
+ "(-1=auto [default], 0=disabled, 1=enabled)");
module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
MODULE_PARM_DESC(enable_psr, "Enable PSR "
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* ✗ Fi.CI.BAT: failure for Add support for GuC-based SLPC (rev2)
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
` (25 preceding siblings ...)
2016-03-09 0:34 ` [PATCH 26/26] DO NOT MERGE: drm/i915: Enable SLPC, " tom.orourke
@ 2016-03-09 8:03 ` Patchwork
26 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2016-03-09 8:03 UTC (permalink / raw)
To: tom.orourke; +Cc: intel-gfx
== Series Details ==
Series: Add support for GuC-based SLPC (rev2)
URL : https://patchwork.freedesktop.org/series/2691/
State : failure
== Summary ==
Series 2691v2 Add support for GuC-based SLPC
http://patchwork.freedesktop.org/api/1.0/series/2691/revisions/2/mbox/
Test drv_getparams_basic:
Subgroup basic-eu-total:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-subslice-total:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Test drv_hangman:
Subgroup error-state-basic:
pass -> DMESG-WARN (bsw-nuc-2)
pass -> SKIP (skl-i5k-2)
pass -> DMESG-WARN (hsw-gt2)
pass -> DMESG-WARN (bdw-ultra)
pass -> SKIP (skl-i7k-2)
pass -> DMESG-WARN (ivb-t430s)
pass -> DMESG-WARN (byt-nuc)
pass -> DMESG-WARN (snb-x220t)
pass -> DMESG-WARN (snb-dellxps)
pass -> DMESG-WARN (hsw-brixbox)
pass -> DMESG-WARN (bdw-nuci7)
Test drv_module_reload_basic:
pass -> DMESG-WARN (bsw-nuc-2)
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-WARN (hsw-gt2)
pass -> DMESG-WARN (bdw-ultra)
pass -> DMESG-FAIL (skl-i7k-2)
pass -> DMESG-WARN (ivb-t430s)
pass -> DMESG-WARN (byt-nuc)
pass -> DMESG-WARN (snb-x220t)
pass -> DMESG-WARN (snb-dellxps)
pass -> DMESG-WARN (hsw-brixbox)
pass -> DMESG-WARN (bdw-nuci7)
Test gem_basic:
Subgroup bad-close:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup create-close:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup create-fd-close:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Test gem_cpu_reloc:
Subgroup basic:
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (skl-i7k-2)
Test gem_cs_tlb:
Subgroup basic-default:
pass -> SKIP (skl-i5k-2)
pass -> DMESG-WARN (snb-x220t)
pass -> SKIP (skl-i7k-2)
Test gem_ctx_basic:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Test gem_ctx_create:
Subgroup basic:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Test gem_ctx_exec:
Subgroup basic:
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (skl-i7k-2)
Test gem_ctx_param_basic:
Subgroup basic:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-default:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup invalid-ctx-get:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup invalid-ctx-set:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup invalid-param-get:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup invalid-param-set:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup invalid-size-get:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup invalid-size-set:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup non-root-set:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup non-root-set-no-zeromap:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup root-set:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup root-set-no-zeromap-disabled:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup root-set-no-zeromap-enabled:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Test gem_exec_basic:
Subgroup basic-blt:
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (skl-i7k-2)
Subgroup basic-bsd:
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (skl-i7k-2)
Subgroup basic-default:
pass -> SKIP (skl-i5k-2)
pass -> SKIP (skl-i7k-2)
Subgroup basic-render:
pass -> SKIP (skl-i5k-2)
pass -> SKIP (skl-i7k-2)
Subgroup basic-vebox:
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (skl-i7k-2)
Subgroup gtt-blt:
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (skl-i7k-2)
Subgroup gtt-bsd:
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (skl-i7k-2)
Subgroup gtt-default:
pass -> SKIP (skl-i5k-2)
pass -> SKIP (skl-i7k-2)
Subgroup gtt-render:
pass -> SKIP (skl-i5k-2)
pass -> SKIP (skl-i7k-2)
Subgroup gtt-vebox:
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (skl-i7k-2)
Subgroup readonly-blt:
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (skl-i7k-2)
Subgroup readonly-bsd:
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (skl-i7k-2)
Subgroup readonly-default:
pass -> SKIP (skl-i5k-2)
pass -> SKIP (skl-i7k-2)
Subgroup readonly-render:
pass -> SKIP (skl-i5k-2)
pass -> SKIP (skl-i7k-2)
Subgroup readonly-vebox:
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (skl-i7k-2)
Test gem_exec_nop:
Subgroup basic:
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (skl-i7k-2)
Test gem_flink_basic:
Subgroup bad-flink:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup bad-open:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup double-flink:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup flink-lifetime:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Test gem_linear_blits:
Subgroup basic:
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (skl-i7k-2)
Test gem_mmap:
Subgroup basic:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-small-bo:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Test gem_mmap_gtt:
Subgroup basic:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-copy:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-read:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-read-no-prefault:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-read-write:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-read-write-distinct:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-short:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-small-bo:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-small-bo-tiledx:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-small-bo-tiledy:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-small-copy:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-small-copy-xy:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-write:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-write-cpu-read-gtt:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-write-gtt:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-write-gtt-no-prefault:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-write-no-prefault:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-write-read:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-write-read-distinct:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Test gem_pread:
Subgroup basic:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Test gem_pwrite:
Subgroup basic:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Test gem_render_linear_blits:
Subgroup basic:
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (skl-i7k-2)
Test gem_render_tiled_blits:
Subgroup basic:
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (skl-i7k-2)
Test gem_ringfill:
Subgroup basic-default:
pass -> SKIP (skl-i5k-2)
pass -> SKIP (skl-i7k-2)
Subgroup basic-default-bomb:
pass -> SKIP (skl-i5k-2)
pass -> SKIP (skl-i7k-2)
Subgroup basic-default-child:
pass -> SKIP (skl-i5k-2)
pass -> SKIP (skl-i7k-2)
Subgroup basic-default-forked:
pass -> SKIP (skl-i5k-2)
pass -> SKIP (skl-i7k-2)
Subgroup basic-default-hang:
pass -> DMESG-WARN (bsw-nuc-2)
pass -> SKIP (skl-i5k-2)
pass -> DMESG-WARN (hsw-gt2)
pass -> DMESG-WARN (bdw-ultra)
pass -> SKIP (skl-i7k-2)
pass -> DMESG-WARN (ivb-t430s)
pass -> DMESG-WARN (byt-nuc)
pass -> DMESG-WARN (snb-x220t)
pass -> DMESG-WARN (snb-dellxps)
pass -> DMESG-WARN (hsw-brixbox)
pass -> DMESG-WARN (bdw-nuci7)
Subgroup basic-default-interruptible:
pass -> SKIP (skl-i5k-2)
pass -> SKIP (skl-i7k-2)
Subgroup basic-default-s3:
pass -> DMESG-WARN (bsw-nuc-2)
pass -> SKIP (skl-i5k-2)
pass -> DMESG-WARN (hsw-gt2)
pass -> DMESG-WARN (bdw-ultra)
pass -> SKIP (skl-i7k-2)
pass -> DMESG-WARN (ivb-t430s)
pass -> DMESG-WARN (byt-nuc)
pass -> DMESG-WARN (snb-x220t)
pass -> DMESG-WARN (snb-dellxps)
pass -> DMESG-WARN (hsw-brixbox)
pass -> DMESG-WARN (bdw-nuci7)
Test gem_storedw_loop:
Subgroup basic-blt:
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (skl-i7k-2)
Subgroup basic-bsd:
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (skl-i7k-2)
Subgroup basic-default:
pass -> SKIP (skl-i5k-2)
pass -> SKIP (skl-i7k-2)
Subgroup basic-render:
pass -> SKIP (skl-i5k-2) UNSTABLE
pass -> SKIP (skl-i7k-2) UNSTABLE
Subgroup basic-vebox:
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (skl-i7k-2)
Test gem_sync:
Subgroup basic-all:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-blt:
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (skl-i7k-2)
Subgroup basic-bsd:
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (skl-i7k-2)
Subgroup basic-default:
pass -> SKIP (skl-i5k-2)
pass -> DMESG-FAIL (hsw-brixbox)
pass -> SKIP (skl-i7k-2)
Subgroup basic-render:
pass -> SKIP (skl-i5k-2) UNSTABLE
pass -> SKIP (skl-i7k-2) UNSTABLE
pass -> DMESG-WARN (ivb-t430s)
Subgroup basic-vebox:
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (skl-i7k-2)
Test gem_tiled_blits:
Subgroup basic:
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (skl-i7k-2)
Test gem_tiled_fence_blits:
Subgroup basic:
pass -> DMESG-FAIL (skl-i5k-2)
pass -> DMESG-FAIL (skl-i7k-2)
Test gem_tiled_pread_basic:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Test kms_addfb_basic:
Subgroup addfb25-bad-modifier:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup addfb25-framebuffer-vs-set-tiling:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup addfb25-modifier-no-flag:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup addfb25-x-tiled:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup addfb25-x-tiled-mismatch:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup addfb25-y-tiled:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup addfb25-y-tiled-small:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup addfb25-yf-tiled:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup bad-pitch-0:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup bad-pitch-1024:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup bad-pitch-128:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup bad-pitch-256:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup bad-pitch-32:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup bad-pitch-63:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup bad-pitch-65536:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup bad-pitch-999:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-x-tiled:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup basic-y-tiled:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup bo-too-small:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup bo-too-small-due-to-tiling:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup clobberred-modifier:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup framebuffer-vs-set-tiling:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup no-handle:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup size-max:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup small-bo:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup tile-pitch-mismatch:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup too-high:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup too-wide:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup unused-handle:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup unused-modifier:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (skl-i7k-2)
Subgroup unused-offsets:
pass -> DMESG-WARN (skl-i5k-2)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2016-03-09 8:03 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-03-09 0:34 [PATCH v2 00/26] Add support for GuC-based SLPC tom.orourke
2016-03-09 0:34 ` [PATCH 01/26] drm/i915/slpc: Expose guc functions for use with SLPC tom.orourke
2016-03-09 0:34 ` [PATCH 02/26] drm/i915/slpc: Add has_slpc capability flag tom.orourke
2016-03-09 0:34 ` [PATCH 03/26] drm/i915/slpc: Add slpc_version_check tom.orourke
2016-03-09 0:34 ` [PATCH 04/26] drm/i915/slpc: Add enable_slpc module parameter tom.orourke
2016-03-09 0:34 ` [PATCH 05/26] drm/i915/slpc: Use intel_slpc_* functions if supported tom.orourke
2016-03-09 0:34 ` [PATCH 06/26] drm/i915/slpc: Enable SLPC in guc " tom.orourke
2016-03-09 0:34 ` [PATCH 07/26] drm/i915/slpc: If using SLPC, do not set frequency tom.orourke
2016-03-09 0:34 ` [PATCH 08/26] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data tom.orourke
2016-03-09 0:34 ` [PATCH 09/26] drm/i915/slpc: Setup rps frequency values during SLPC init tom.orourke
2016-03-09 0:34 ` [PATCH 10/26] drm/i915/slpc: Update current requested frequency tom.orourke
2016-03-09 0:34 ` [PATCH 11/26] drm/i915/slpc: Send reset event tom.orourke
2016-03-09 0:34 ` [PATCH 12/26] drm/i915/slpc: Send shutdown event tom.orourke
2016-03-09 0:34 ` [PATCH 13/26] drm/i915/slpc: Add Display mode event related data structures tom.orourke
2016-03-09 0:34 ` [PATCH 14/26] drm/i915/slpc: Notification of Display mode change tom.orourke
2016-03-09 0:34 ` [PATCH 15/26] drm/i915/slpc: Notification of Refresh Rate change tom.orourke
2016-03-09 0:34 ` [PATCH 16/26] drm/i915/slpc: Add slpc_status enum values tom.orourke
2016-03-09 0:34 ` [PATCH 17/26] drm/i915/slpc: Add parameter unset/set/get functions tom.orourke
2016-03-09 0:34 ` [PATCH 18/26] drm/i915/slpc: Add slpc support for max/min freq tom.orourke
2016-03-09 0:34 ` [PATCH 19/26] drm/i915/slpc: Add enable/disable debugfs for slpc tom.orourke
2016-03-09 0:34 ` [PATCH 20/26] drm/i915/slpc: Add broxton support tom.orourke
2016-03-09 0:34 ` [PATCH 21/26] drm/i915/slpc: Add i915_slpc_info to debugfs tom.orourke
2016-03-09 0:34 ` [PATCH 22/26] DO NOT MERGE: drm/i915: Change SKL guc version wanted to 6.0 tom.orourke
2016-03-09 0:34 ` [PATCH 23/26] DO NOT MERGE: drm/i915/bxt: Add Broxton to guc loader tom.orourke
2016-03-09 0:34 ` [PATCH 24/26] DO NOT MERGE: drm/i915: resize the GuC WOPCM for rc6 tom.orourke
2016-03-09 0:34 ` [PATCH 25/26] DO NOT MERGE: drm/i915: Enable GuC submission, where supported tom.orourke
2016-03-09 0:34 ` [PATCH 26/26] DO NOT MERGE: drm/i915: Enable SLPC, " tom.orourke
2016-03-09 8:03 ` ✗ Fi.CI.BAT: failure for Add support for GuC-based SLPC (rev2) Patchwork
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