From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 08/16] drm/i915/skl: Unexport skl_pw1_misc_io_init
Date: Fri, 1 Apr 2016 16:02:39 +0300 [thread overview]
Message-ID: <1459515767-29228-9-git-send-email-imre.deak@intel.com> (raw)
In-Reply-To: <1459515767-29228-1-git-send-email-imre.deak@intel.com>
On Broxton we need to enable/disable power well 1 during the init/unit display
sequence similarly to Skylake/Kabylake. The code for this will be added in a
follow-up patch, but to prepare for that unexport skl_pw1_misc_io_init(). It's
a simple function called only from a single place and having it inlined in the
Skylake display core init/unit functions will make it easier to compare it
with its Broxton counterpart.
No functional change.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_drv.h | 2 --
drivers/gpu/drm/i915/intel_runtime_pm.c | 49 ++++++++++++---------------------
2 files changed, 18 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9255b56..8ba2ac3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1460,8 +1460,6 @@ int intel_power_domains_init(struct drm_i915_private *);
void intel_power_domains_fini(struct drm_i915_private *);
void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
-void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv);
-void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv);
void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
const char *
intel_display_power_domain_str(enum intel_display_power_domain domain);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index b16315e..58ed8bc 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1921,34 +1921,6 @@ static struct i915_power_well skl_power_wells[] = {
},
};
-void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv)
-{
- struct i915_power_well *well;
-
- if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
- return;
-
- well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
- intel_power_well_enable(dev_priv, well);
-
- well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
- intel_power_well_enable(dev_priv, well);
-}
-
-void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv)
-{
- struct i915_power_well *well;
-
- if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
- return;
-
- well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
- intel_power_well_disable(dev_priv, well);
-
- well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
- intel_power_well_disable(dev_priv, well);
-}
-
static struct i915_power_well bxt_power_wells[] = {
{
.name = "always-on",
@@ -2139,9 +2111,10 @@ static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
}
static void skl_display_core_init(struct drm_i915_private *dev_priv,
- bool resume)
+ bool resume)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_well *well;
uint32_t val;
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
@@ -2152,7 +2125,13 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
/* enable PG1 and Misc I/O */
mutex_lock(&power_domains->lock);
- skl_pw1_misc_io_init(dev_priv);
+
+ well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
+ intel_power_well_enable(dev_priv, well);
+
+ well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
+ intel_power_well_enable(dev_priv, well);
+
mutex_unlock(&power_domains->lock);
if (!resume)
@@ -2167,6 +2146,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_well *well;
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
@@ -2174,8 +2154,15 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
/* The spec doesn't call for removing the reset handshake flag */
/* disable PG1 and Misc I/O */
+
mutex_lock(&power_domains->lock);
- skl_pw1_misc_io_fini(dev_priv);
+
+ well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
+ intel_power_well_enable(dev_priv, well);
+
+ well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
+ intel_power_well_enable(dev_priv, well);
+
mutex_unlock(&power_domains->lock);
}
--
2.5.0
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next prev parent reply other threads:[~2016-04-01 13:03 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-01 13:02 [PATCH 00/16] drm/i915/bxt: Fix/enable display power well support/runtime PM Imre Deak
2016-04-01 13:02 ` [PATCH 01/16] drm/i915/bxt: Reject DMC firmware versions with known bugs Imre Deak
2016-04-11 12:39 ` Mika Kuoppala
2016-04-01 13:02 ` [PATCH 02/16] drm/i915/bxt: Fix GRC code register field definitions Imre Deak
2016-04-08 17:22 ` Ville Syrjälä
2016-04-08 17:27 ` Imre Deak
2016-04-01 13:02 ` [PATCH 03/16] drm/i915/bxt: Add a note about BXT_PORT_CL1CM_DW30 being read-only Imre Deak
2016-04-08 18:02 ` Ville Syrjälä
2016-04-08 18:12 ` Imre Deak
2016-04-08 18:16 ` Imre Deak
2016-04-12 15:11 ` David Weinehall
2016-04-01 13:02 ` [PATCH 04/16] drm/i915/bxt: Reset secondary power well requests left on by DMC/KVMR Imre Deak
2016-04-05 10:26 ` [PATCH v2 04/16] drm/i915/gen9: " Imre Deak
2016-04-06 10:59 ` Patrik Jakobsson
2016-04-01 13:02 ` [PATCH 05/16] drm/i915/gen9: Make power well disabling synchronous Imre Deak
2016-04-04 10:34 ` Patrik Jakobsson
2016-04-05 8:26 ` Patrik Jakobsson
2016-04-05 9:30 ` Imre Deak
2016-04-01 13:02 ` [PATCH 06/16] drm/i915/gen9: Fix DMC/DC state asserts Imre Deak
2016-04-04 10:52 ` Patrik Jakobsson
2016-04-01 13:02 ` [PATCH 07/16] drm/i915/bxt: Suspend power domains during suspend-to-idle Imre Deak
2016-04-04 11:28 ` Patrik Jakobsson
2016-04-01 13:02 ` Imre Deak [this message]
2016-04-04 12:30 ` [PATCH 08/16] drm/i915/skl: Unexport skl_pw1_misc_io_init Patrik Jakobsson
2016-04-04 12:34 ` Imre Deak
2016-04-04 12:42 ` [PATCH v2 " Imre Deak
2016-04-04 13:01 ` Patrik Jakobsson
2016-04-04 13:54 ` Imre Deak
2016-04-01 13:02 ` [PATCH 09/16] drm/i915/bxt: Pass drm_i915_private to DDI PHY, CDCLK helpers Imre Deak
2016-04-08 18:03 ` Ville Syrjälä
2016-04-12 15:12 ` David Weinehall
2016-04-01 13:02 ` [PATCH 10/16] drm/i915/bxt: Power down DDI PHYs separately during the per PHY uninit Imre Deak
2016-04-01 13:29 ` Jani Nikula
2016-04-01 13:40 ` Imre Deak
2016-04-08 18:04 ` Ville Syrjälä
2016-04-01 13:02 ` [PATCH 11/16] drm/i915/bxt: Don't toggle power well 1 on-demand Imre Deak
2016-04-08 18:10 ` Ville Syrjälä
2016-04-01 13:02 ` [PATCH 12/16] drm/i915/bxt: Sanitize the DBUF HW state together with CDCLK Imre Deak
2016-04-11 13:19 ` Mika Kuoppala
2016-04-01 13:02 ` [PATCH 13/16] drm/i915/bxt: Don't reprogram an already enabled DDI PHY Imre Deak
2016-04-08 18:15 ` Ville Syrjälä
2016-04-01 13:02 ` [PATCH 14/16] drm/i915/bxt: Add HW state verification for DDI PHY and CDCLK Imre Deak
2016-04-01 14:28 ` [PATCH v2 " Imre Deak
2016-04-04 14:27 ` [PATCH v3 " Imre Deak
2016-04-12 15:21 ` David Weinehall
2016-04-01 13:02 ` [PATCH 15/16] Revert "drm/i915/bxt: Disable power well support" Imre Deak
2016-04-12 15:22 ` David Weinehall
2016-04-01 13:02 ` [PATCH 16/16] drm/i915/bxt: Enable runtime PM Imre Deak
2016-04-12 15:21 ` David Weinehall
2016-04-01 13:45 ` ✗ Fi.CI.BAT: failure for drm/i915/bxt: Fix/enable display power well support/runtime PM Patchwork
2016-04-01 14:35 ` ✓ Fi.CI.BAT: success for drm/i915/bxt: Fix/enable display power well support/runtime PM (rev2) Patchwork
2016-04-04 14:07 ` ✗ Fi.CI.BAT: failure for drm/i915/bxt: Fix/enable display power well support/runtime PM (rev3) Patchwork
2016-04-04 15:56 ` ✗ Fi.CI.BAT: failure for drm/i915/bxt: Fix/enable display power well support/runtime PM (rev4) Patchwork
2016-04-05 12:19 ` ✓ Fi.CI.BAT: success for drm/i915/bxt: Fix/enable display power well support/runtime PM (rev5) Patchwork
2016-04-15 12:06 ` Imre Deak
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