[PATCH 18/25] drm/i915/slpc: Add slpc support for max/min freq

tom.orourke
2016-04-06T19:24:58Z

Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.

v2: Update for SLPC 2015.2.4 (params for both slice and unslice)
Replace HAS_SLPC with intel_slpc_active() (Paulo)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 16 ++++++++++++++++
drivers/gpu/drm/i915/i915_sysfs.c | 18 ++++++++++++++++++
2 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d844ac8..5f0d72b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4970,6 +4970,14 @@ i915_max_freq_set(void *data, u64 val)
}

dev_priv->rps.max_freq_softlimit = val;
+ if (intel_slpc_active(dev)) {
+ intel_slpc_set_param(dev,
+ SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(dev,
+ SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ }

intel_set_rps(dev, val);

@@ -5037,6 +5045,14 @@ i915_min_freq_set(void *data, u64 val)
}

dev_priv->rps.min_freq_softlimit = val;
+ if (intel_slpc_active(dev)) {
+ intel_slpc_set_param(dev,
+ SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(dev,
+ SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ }

intel_set_rps(dev, val);

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 923a63a..7b8e73e 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -392,6 +392,15 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,

dev_priv->rps.max_freq_softlimit = val;

+ if (intel_slpc_active(dev)) {
+ intel_slpc_set_param(dev,
+ SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(dev,
+ SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ }
+
val = clamp_t(int, dev_priv->rps.cur_freq,
dev_priv->rps.min_freq_softlimit,
dev_priv->rps.max_freq_softlimit);
@@ -456,6 +465,15 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,

dev_priv->rps.min_freq_softlimit = val;

+ if (intel_slpc_active(dev)) {
+ intel_slpc_set_param(dev,
+ SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(dev,
+ SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ }
+
val = clamp_t(int, dev_priv->rps.cur_freq,
dev_priv->rps.min_freq_softlimit,
dev_priv->rps.max_freq_softlimit);