From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 02/16] drm/i915/bxt: Fix GRC code register field definitions Date: Fri, 08 Apr 2016 20:27:27 +0300 Message-ID: <1460136447.13613.7.camel@intel.com> References: <1459515767-29228-1-git-send-email-imre.deak@intel.com> <1459515767-29228-3-git-send-email-imre.deak@intel.com> <20160408172211.GR4329@intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 699EE6E083 for ; Fri, 8 Apr 2016 17:27:29 +0000 (UTC) In-Reply-To: <20160408172211.GR4329@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ville =?ISO-8859-1?Q?Syrj=E4l=E4?= Cc: intel-gfx@lists.freedesktop.org, Arthur J Runyan List-Id: intel-gfx@lists.freedesktop.org T24gcGUsIDIwMTYtMDQtMDggYXQgMjA6MjIgKzAzMDAsIFZpbGxlIFN5cmrDpGzDpCB3cm90ZToK PiBPbiBGcmksIEFwciAwMSwgMjAxNiBhdCAwNDowMjozM1BNICswMzAwLCBJbXJlIERlYWsgd3Jv dGU6Cj4gPiBUaGlzIGhhcyBiZWVuIGNvcnJlY3RlZCBpbiBCU3BlYyBxdWl0ZSBzb21lIHRpbWUg YWdvLCBidXQgd2UgbWlzc2VkCj4gPiBpdAo+ID4gc29tZWhvdy4gVGhlIHdyb25nIGZpZWxkIGRl ZmluaXRpb25zIHJlc3VsdGVkIGluIGNvbmZpZ3VyaW5nIFBIWTAKPiA+IHdpdGgKPiA+IGFuIGlu Y29ycmVjdCBHUkMgdmFsdWUuCj4gPiAKPiA+IENDOiBBcnRodXIgSiBSdW55YW4gPGFydGh1ci5q LnJ1bnlhbkBpbnRlbC5jb20+Cj4gPiBTaWduZWQtb2ZmLWJ5OiBJbXJlIERlYWsgPGltcmUuZGVh a0BpbnRlbC5jb20+Cj4gPiAtLS0KPiA+IMKgZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9yZWcu aCB8IDYgKysrLS0tCj4gPiDCoDEgZmlsZSBjaGFuZ2VkLCAzIGluc2VydGlvbnMoKyksIDMgZGVs ZXRpb25zKC0pCj4gPiAKPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pOTE1 X3JlZy5oCj4gPiBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfcmVnLmgKPiA+IGluZGV4IDZk ZjNjNTkuLmY0YTkxYmIgMTAwNjQ0Cj4gPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pOTE1 X3JlZy5oCj4gPiArKysgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pOTE1X3JlZy5oCj4gPiBAQCAt MTM3MywxMCArMTM3MywxMCBAQCBlbnVtIHNrbF9kaXNwX3Bvd2VyX3dlbGxzIHsKPiA+IMKgICog RklYTUU6IEJTcGVjL0NIViBDb25maWdEQiBkaXNhZ3JlZXMgb24gdGhlIGZvbGxvd2luZyB0d28K PiA+IGZpZWxkcywgZml4IHRoZW0KPiA+IMKgICogYWZ0ZXIgdGVzdGluZy4KPiA+IMKgICovCj4g Cj4gVGhlIEZJWE1FIGNhbiBnbywgbm8/CgpBaCB5ZWEgd2lsbCByZW1vdmUgaXQuIFNvIHdlIGRp ZCB0aGluayBhYm91dCB0aGlzIGFscmVhZHkgZWFybGllci4uCgo+IE1hdGNoZXMgbXkgUEhZIGRv Y3MgYXMgd2VsbCBhcyBic3BlYyBub3cuCj4gCj4gUmV2aWV3ZWQtYnk6IFZpbGxlIFN5cmrDpGzD pCA8dmlsbGUuc3lyamFsYUBsaW51eC5pbnRlbC5jb20+Cj4gCj4gPiAtI2RlZmluZcKgwqDCoEdS Q19DT0RFX1NISUZUCQkyMwo+ID4gLSNkZWZpbmXCoMKgwqBHUkNfQ09ERV9NQVNLCQkJKDB4MUZG IDw8Cj4gPiBHUkNfQ09ERV9TSElGVCkKPiA+ICsjZGVmaW5lwqDCoMKgR1JDX0NPREVfU0hJRlQJ CTI0Cj4gPiArI2RlZmluZcKgwqDCoEdSQ19DT0RFX01BU0sJCQkoMHhGRiA8PAo+ID4gR1JDX0NP REVfU0hJRlQpCj4gPiDCoCNkZWZpbmXCoMKgwqBHUkNfQ09ERV9GQVNUX1NISUZUCQkxNgo+ID4g LSNkZWZpbmXCoMKgwqBHUkNfQ09ERV9GQVNUX01BU0sJCSgweDdGIDw8Cj4gPiBHUkNfQ09ERV9G QVNUX1NISUZUKQo+ID4gKyNkZWZpbmXCoMKgwqBHUkNfQ09ERV9GQVNUX01BU0sJCSgweEZGIDw8 Cj4gPiBHUkNfQ09ERV9GQVNUX1NISUZUKQo+ID4gwqAjZGVmaW5lwqDCoMKgR1JDX0NPREVfU0xP V19TSElGVAkJOAo+ID4gwqAjZGVmaW5lwqDCoMKgR1JDX0NPREVfU0xPV19NQVNLCQkoMHhGRiA8 PAo+ID4gR1JDX0NPREVfU0xPV19TSElGVCkKPiA+IMKgI2RlZmluZcKgwqDCoEdSQ19DT0RFX05P TV9NQVNLCQkweEZGCj4gPiAtLSAKPiA+IDIuNS4wCj4gPiAKPiA+IF9fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCj4gPiBJbnRlbC1nZnggbWFpbGluZyBsaXN0 Cj4gPiBJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCj4gPiBodHRwczovL2xpc3RzLmZy ZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ludGVsLWdmeAo+IApfX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpJbnRlbC1nZnggbWFpbGluZyBsaXN0 CkludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3Rv cC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngK