From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: stable@vger.kernel.org
Subject: [PATCH v3 1/3] drm/i915/bdw: Add missing delay during L3 SQC credit programming
Date: Tue, 3 May 2016 15:54:19 +0300 [thread overview]
Message-ID: <1462280061-1457-2-git-send-email-imre.deak@intel.com> (raw)
In-Reply-To: <1462280061-1457-1-git-send-email-imre.deak@intel.com>
BSpec requires us to wait ~100 clocks before re-enabling clock gating,
so make sure we do this.
CC: stable@vger.kernel.org
CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2422ac3..227cd2d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6738,6 +6738,12 @@ static void broadwell_init_clock_gating(struct drm_device *dev)
misccpctl = I915_READ(GEN7_MISCCPCTL);
I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
+ /*
+ * Wait at least 100 clocks before re-enabling clock gating. See
+ * the definition of L3SQCREG1 in BSpec.
+ */
+ POSTING_READ(GEN8_L3SQCREG1);
+ udelay(1);
I915_WRITE(GEN7_MISCCPCTL, misccpctl);
/*
--
2.5.0
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next prev parent reply other threads:[~2016-05-03 12:54 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-03 12:54 [PATCH v3 0/3] drm/i915: Tune the GPU L3 SQ credits on CHV Imre Deak
2016-05-03 12:54 ` Imre Deak [this message]
2016-05-03 12:54 ` [PATCH v3 2/3] drm/i915: Clean up L3 SQC register field definitions Imre Deak
2016-05-03 12:54 ` [PATCH v3 3/3] drm/i915/chv: Tune L3 SQC credits based on actual latencies Imre Deak
2016-05-03 13:18 ` ✗ Fi.CI.BAT: failure for drm/i915: Tune the GPU L3 SQ credits on CHV Patchwork
2016-05-03 13:55 ` Imre Deak
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