From: Imre Deak <imre.deak@intel.com>
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 09/21] drm/i915: Beef up skl_sanitize_cdclk() a bit
Date: Thu, 19 May 2016 17:30:38 +0300 [thread overview]
Message-ID: <1463668238.12342.38.camel@intel.com> (raw)
In-Reply-To: <1463172100-24715-10-git-send-email-ville.syrjala@linux.intel.com>
On pe, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Also verify the DPLL_CTRL1 register value in skl_sanitize_cdclk(), throw
> out a few unneeded variables, and write the CDCLK_CTL check a bit more
> legible way.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 18 +++++++++++++-----
> 1 file changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 107a7799bdde..493160682b2a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5789,9 +5789,7 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
>
> int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> {
> - uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
> - uint32_t cdctl = I915_READ(CDCLK_CTL);
> - int freq = dev_priv->cdclk_freq;
> + uint32_t cdctl, expected;
>
> /*
> * check if the pre-os intialized the display
> @@ -5802,7 +5800,14 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> goto sanitize;
>
> /* Is PLL enabled and locked ? */
> - if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
> + if ((I915_READ(LCPLL1_CTL) & (LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK)) !=
> + (LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK))
> + goto sanitize;
> +
> + if ((I915_READ(DPLL_CTRL1) & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
> + DPLL_CTRL1_SSC(SKL_DPLL0) |
> + DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
> + DPLL_CTRL1_OVERRIDE(SKL_DPLL0))
> goto sanitize;
>
> /* DPLL okay; verify the cdclock
> @@ -5811,7 +5816,10 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> * decimal part is programmed wrong from BIOS where pre-os does not
> * enable display. Verify the same as well.
> */
> - if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
> + cdctl = I915_READ(CDCLK_CTL);
> + expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
> + skl_cdclk_decimal(dev_priv->cdclk_freq);
> + if (cdctl == expected)
> /* All well; nothing to sanitize */
> return false;
> sanitize:
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next prev parent reply other threads:[~2016-05-19 14:30 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-13 20:41 [PATCH 00/21] drm/i915: SKL/KBL/BXT cdclk stuff ville.syrjala
2016-05-13 20:41 ` [PATCH 01/21] drm/i915: Fix BXT min_pixclk after state readout ville.syrjala
2016-05-17 18:09 ` Imre Deak
2016-05-17 18:21 ` Ville Syrjälä
2016-05-17 18:24 ` Imre Deak
2016-05-13 20:41 ` [PATCH 02/21] drm/i915/skl: SKL CDCLK change on modeset tracking VCO ville.syrjala
2016-05-19 9:08 ` Imre Deak
2016-05-19 9:18 ` Ville Syrjälä
2016-05-13 20:41 ` [PATCH 03/21] drm/i915: Move the SKL DPLL0 VCO computation into intel_dp_compute_config() ville.syrjala
2016-05-19 11:57 ` Imre Deak
2016-05-13 20:41 ` [PATCH 04/21] drm/i915: Extract skl_calc_cdclk() ville.syrjala
2016-05-19 12:02 ` Imre Deak
2016-05-13 20:41 ` [PATCH 05/21] drm/i915: Actually read out DPLL0 vco on skl from hardware ville.syrjala
2016-05-19 12:38 ` Imre Deak
2016-05-13 20:41 ` [PATCH 06/21] drm/i915: Report the current DPLL0 vco on SKL/KBL ville.syrjala
2016-05-19 12:40 ` Imre Deak
2016-05-13 20:41 ` [PATCH 07/21] drm/i915: Allow enable/disable of DPLL0 around cdclk changes on SKL ville.syrjala
2016-05-19 13:04 ` Imre Deak
2016-05-19 13:18 ` Ville Syrjälä
2016-05-19 13:39 ` Imre Deak
2016-05-13 20:41 ` [PATCH 08/21] drm/i915: Keep track of preferred cdclk vco frequency " ville.syrjala
2016-05-19 14:25 ` Imre Deak
2016-05-13 20:41 ` [PATCH 09/21] drm/i915: Beef up skl_sanitize_cdclk() a bit ville.syrjala
2016-05-19 14:30 ` Imre Deak [this message]
2016-05-13 20:41 ` [PATCH 10/21] drm/i915: Unify SKL cdclk init paths ville.syrjala
2016-05-19 15:43 ` Imre Deak
2016-05-23 18:20 ` Ville Syrjälä
2016-05-13 20:41 ` [PATCH 11/21] drm/i915: Move SKL+ DBUF enable/disable to display core init/uninit ville.syrjala
2016-05-19 15:48 ` Imre Deak
2016-05-23 18:20 ` Ville Syrjälä
2016-05-13 20:41 ` [PATCH 12/21] drm/i915: Make 308 and 671 MHz cdclks more accurate on SKL ville.syrjala
2016-05-19 16:03 ` Imre Deak
2016-05-13 20:41 ` [PATCH 13/21] drm/i915: Rename skl_vco_freq to cdclk_pll.vco ville.syrjala
2016-05-19 16:17 ` Imre Deak
2016-05-19 16:21 ` Ville Syrjälä
2016-05-13 20:41 ` [PATCH 14/21] drm/i915: Store cdclk PLL reference clock under dev_priv ville.syrjala
2016-05-19 17:00 ` Imre Deak
2016-05-13 20:41 ` [PATCH 15/21] drm/i915: Extract bxt DE PLL enable/disable from broxton_set_cdclk() ville.syrjala
2016-05-19 17:04 ` Imre Deak
2016-05-13 20:41 ` [PATCH 16/21] drm/i915: Store BXT DE PLL vco and ref clocks in dev_priv ville.syrjala
2016-05-19 18:43 ` Imre Deak
2016-05-13 20:41 ` [PATCH 17/21] drm/i915: Update cached cdclk state from broxton_init_cdclk() ville.syrjala
2016-05-19 18:46 ` Imre Deak
2016-05-13 20:41 ` [PATCH 18/21] drm/i915: Rewrite broxton_get_display_clock_speed() in terms of the DE PLL vco/refclk ville.syrjala
2016-05-19 19:05 ` Imre Deak
2016-05-13 20:41 ` [PATCH 19/21] drm/i915: Make bxt_set_cdclk() operate in terms of the current vs target DE PLL vco ville.syrjala
2016-05-19 19:40 ` Imre Deak
2016-05-13 20:41 ` [PATCH 20/21] drm/i915: Replace bxt_verify_cdclk_state() with a more generic cdclk check ville.syrjala
2016-05-19 19:41 ` Imre Deak
2016-05-13 20:41 ` [PATCH 21/21] drm/i915: Set BXT cdclk to minimum initially ville.syrjala
2016-05-19 19:45 ` Imre Deak
2016-05-14 5:25 ` ✗ Ro.CI.BAT: failure for drm/i915: SKL/KBL/BXT cdclk stuff Patchwork
2016-05-23 17:25 ` Ville Syrjälä
2016-05-16 13:59 ` [PATCH 22/21] drm/i915: Assert the dbuf is enabled when disabling DC5/6 ville.syrjala
2016-05-19 19:49 ` Imre Deak
2016-05-23 18:21 ` Ville Syrjälä
2016-05-23 18:21 ` [PATCH 00/21] drm/i915: SKL/KBL/BXT cdclk stuff Ville Syrjälä
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