[PATCH v2 1/2] drm/i915/gen9: Assume CDCLK PLL is off if it's not locked

[PATCH v2 1/2] drm/i915/gen9: Assume CDCLK PLL is off if it's not locked

[Imre Deak]

If the CDCLK PLL isn't locked or incorrectly configured we can just
assume that it's off resulting in fully re-initializing both CDCLK PLL
and CDCLK dividers. This way the CDCLK PLL sanitization added in the
following patch can be done on BXT the same way as it's done on SKL.

v2: (Ville)
- Remove the remaining PLL specific checks from skl_sanitize_cdclk() and
  depend instead on the corresponding check in skl_dpll0_update().
- Use vco == 0 instead of the corresponding boolean check in
  skl_sanitize_cdclk().

CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 39 +++++++++++++++---------------------
 1 file changed, 16 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c1e666b..47b2466 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5461,21 +5461,22 @@ skl_dpll0_update(struct drm_i915_private *dev_priv)
 	u32 val;
 
 	dev_priv->cdclk_pll.ref = 24000;
+	dev_priv->cdclk_pll.vco = 0;
 
 	val = I915_READ(LCPLL1_CTL);
-	if ((val & LCPLL_PLL_ENABLE) == 0) {
-		dev_priv->cdclk_pll.vco = 0;
+	if ((val & LCPLL_PLL_ENABLE) == 0)
 		return;
-	}
 
-	WARN_ON((val & LCPLL_PLL_LOCK) == 0);
+	if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
+		return;
 
 	val = I915_READ(DPLL_CTRL1);
 
-	WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
-			DPLL_CTRL1_SSC(SKL_DPLL0) |
-			DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
-		DPLL_CTRL1_OVERRIDE(SKL_DPLL0));
+	if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
+			    DPLL_CTRL1_SSC(SKL_DPLL0) |
+			    DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
+		    DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
+		return;
 
 	switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
 	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
@@ -5490,7 +5491,6 @@ skl_dpll0_update(struct drm_i915_private *dev_priv)
 		break;
 	default:
 		MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
-		dev_priv->cdclk_pll.vco = 0;
 		break;
 	}
 }
@@ -5690,19 +5690,12 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 	if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
 		goto sanitize;
 
+	intel_update_cdclk(dev_priv->dev);
 	/* Is PLL enabled and locked ? */
-	if ((I915_READ(LCPLL1_CTL) & (LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK)) !=
-	    (LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK))
+	if (dev_priv->cdclk_pll.vco == 0 ||
+	    dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
 		goto sanitize;
 
-	if ((I915_READ(DPLL_CTRL1) & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
-				      DPLL_CTRL1_SSC(SKL_DPLL0) |
-				      DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
-	    DPLL_CTRL1_OVERRIDE(SKL_DPLL0))
-		goto sanitize;
-
-	intel_update_cdclk(dev_priv->dev);
-
 	/* DPLL okay; verify the cdclock
 	 *
 	 * Noticed in some instances that the freq selection is correct but
@@ -6608,14 +6601,14 @@ static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
 	u32 val;
 
 	dev_priv->cdclk_pll.ref = 19200;
+	dev_priv->cdclk_pll.vco = 0;
 
 	val = I915_READ(BXT_DE_PLL_ENABLE);
-	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) {
-		dev_priv->cdclk_pll.vco = 0;
+	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
 		return;
-	}
 
-	WARN_ON((val & BXT_DE_PLL_LOCK) == 0);
+	if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
+		return;
 
 	val = I915_READ(BXT_DE_PLL_CTL);
 	dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
-- 
2.5.0

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[PATCH v2 2/2] drm/i915/bxt: Sanitize CDCLK to fix breakage during S4 resume

[Imre Deak]

I noticed that during S4 resume BIOS incorrectly sets bits 18, 19 which
are reserved/MBZ and sets the decimal frequency fields to all 0xff in
the CDCLK register. The result is a hard lockup as display register
accesses are attempted later. Work around this by sanitizing the CDCLK
PLL/dividers the same way it's done on SKL.

While this is clearly a BIOS bug which should be fixed separately, it
doesn't hurt to check/sanitize this regardless.

v2:
- Use the same condition for VCO and CDCLK in broxton_init_cdclk as is
  used in skl_init_cdclk for the same purpose.

CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 51 ++++++++++++++++++++++++++++++++++--
 1 file changed, 49 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 47b2466..19f947f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5412,11 +5412,58 @@ static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
 	intel_update_cdclk(dev_priv->dev);
 }
 
+static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
+{
+	u32 cdctl, expected;
+
+	intel_update_cdclk(dev_priv->dev);
+
+	if (dev_priv->cdclk_pll.vco == 0 ||
+	    dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
+		goto sanitize;
+
+	/* DPLL okay; verify the cdclock
+	 *
+	 * Some BIOS versions leave an incorrect decimal frequency value and
+	 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
+	 * so sanitize this register.
+	 */
+	cdctl = I915_READ(CDCLK_CTL);
+	/*
+	 * Let's ignore the pipe field, since BIOS could have configured the
+	 * dividers both synching to an active pipe, or asynchronously
+	 * (PIPE_NONE).
+	 */
+	cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
+
+	expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
+		   skl_cdclk_decimal(dev_priv->cdclk_freq);
+	/*
+	 * Disable SSA Precharge when CD clock frequency < 500 MHz,
+	 * enable otherwise.
+	 */
+	if (dev_priv->cdclk_freq >= 500000)
+		expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
+
+	if (cdctl == expected)
+		/* All well; nothing to sanitize */
+		return;
+
+sanitize:
+	DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
+
+	/* force cdclk programming */
+	dev_priv->cdclk_freq = 0;
+
+	/* force full PLL disable + enable */
+	dev_priv->cdclk_pll.vco = -1;
+}
+
 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
 {
-	intel_update_cdclk(dev_priv->dev);
+	bxt_sanitize_cdclk(dev_priv);
 
-	if (dev_priv->cdclk_pll.vco != 0)
+	if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
 		return;
 
 	/*
-- 
2.5.0

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✗ Ro.CI.BAT: failure for series starting with [v2,1/2] drm/i915/gen9: Assume CDCLK PLL is off if it's not locked

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] drm/i915/gen9: Assume CDCLK PLL is off if it's not locked
URL   : https://patchwork.freedesktop.org/series/7631/
State : failure

== Summary ==

Series 7631v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/7631/revisions/1/mbox

Test gem_busy:
        Subgroup basic-parallel-vebox:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test gem_exec_basic:
        Subgroup readonly-vebox:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_exec_flush:
        Subgroup basic-batch-kernel-default-cmd:
                pass       -> FAIL       (ro-byt-n2820)
Test gem_exec_store:
        Subgroup basic-bsd:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_ringfill:
        Subgroup basic-default-interruptible:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test gem_storedw_loop:
        Subgroup basic-default:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test kms_pipe_crc_basic:
        Subgroup bad-pipe:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test kms_psr_sink_crc:
        Subgroup psr_basic:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test kms_setmode:
        Subgroup basic-clone-single-crtc:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test pm_rpm:
        Subgroup basic-pci-d3-state:
                fail       -> DMESG-WARN (ro-skl-i7-6700hq)

ro-bdw-i5-5250u  total:209  pass:172  dwarn:0   dfail:0   fail:0   skip:37 
ro-bdw-i7-5557U  total:209  pass:197  dwarn:0   dfail:0   fail:0   skip:12 
ro-bdw-i7-5600u  total:209  pass:180  dwarn:0   dfail:0   fail:1   skip:28 
ro-byt-n2820     total:209  pass:169  dwarn:0   dfail:0   fail:3   skip:37 
ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-hsw-i7-4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-ilk-i7-620lm  total:209  pass:146  dwarn:0   dfail:0   fail:1   skip:62 
ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
ro-ivb-i7-3770   total:209  pass:177  dwarn:0   dfail:0   fail:0   skip:32 
ro-ivb2-i7-3770  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
ro-skl-i7-6700hq total:204  pass:175  dwarn:8   dfail:0   fail:0   skip:21 
ro-snb-i7-2620M  total:209  pass:170  dwarn:0   dfail:0   fail:1   skip:38 

Results at /archive/results/CI_IGT_test/RO_Patchwork_993/

8621fb5 drm-intel-nightly: 2016y-05m-23d-18h-18m-33s UTC integration manifest
a416d47 drm/i915/bxt: Sanitize CDCLK to fix breakage during S4 resume
c1d96b1 drm/i915/gen9: Assume CDCLK PLL is off if it's not locked

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Re: ✗ Ro.CI.BAT: failure for series starting with [v2,1/2] drm/i915/gen9: Assume CDCLK PLL is off if it's not locked

[Imre Deak]

On ti, 2016-05-24 at 13:02 +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: series starting with [v2,1/2] drm/i915/gen9: Assume CDCLK PLL
> is off if it's not locked
> URL   : https://patchwork.freedesktop.org/series/7631/
> State : failure
> 
> == Summary ==
> 
> Series 7631v1 Series without cover letter
> http://patchwork.freedesktop.org/api/1.0/series/7631/revisions/1/mbox
> 
> Test gem_busy:
>         Subgroup basic-parallel-vebox:
>                 dmesg-warn -> PASS       (ro-skl-i7-6700hq)
> Test gem_exec_basic:
>         Subgroup readonly-vebox:
>                 pass       -> DMESG-WARN (ro-skl-i7-6700hq)

[drm:intel_pipe_update_start [i915]] *ERROR* Potential atomic update failure on pipe A

https://bugs.freedesktop.org/show_bug.cgi?id=95632

> Test gem_exec_flush:
>         Subgroup basic-batch-kernel-default-cmd:
>                 pass       -> FAIL       (ro-byt-n2820)

Stack trace:
  #0 [__igt_fail_assert+0x101]
  #1 [gem_execbuf+0x44]
  #2 [batch+0x4bd]
  #3 [__real_main481+0x308]
  #4 [main+0x23]
  #5 [__libc_start_main+0xf0]
  #6 [_start+0x29]
  #7 [<unknown>+0x29]
child 0 failed with exit status 99

(gem_exec_flush:6087) ioctl-wrappers-CRITICAL: Failed assertion: __gem_execbuf(fd, execbuf) == 0
(gem_exec_flush:6087) ioctl-wrappers-CRITICAL: error: -22 != 0
Subtest basic-batch-kernel-default-cmd failed.

https://bugs.freedesktop.org/show_bug.cgi?id=95372

> Test gem_exec_store:
>         Subgroup basic-bsd:
>                 pass       -> DMESG-WARN (ro-skl-i7-6700hq)
> Test gem_ringfill:
>         Subgroup basic-default-interruptible:
>                 dmesg-warn -> PASS       (ro-skl-i7-6700hq)
> Test gem_storedw_loop:
>         Subgroup basic-default:
>                 dmesg-warn -> PASS       (ro-skl-i7-6700hq)
> Test kms_pipe_crc_basic:
>         Subgroup bad-pipe:
>                 dmesg-warn -> PASS       (ro-skl-i7-6700hq)
> Test kms_psr_sink_crc:
>         Subgroup psr_basic:
>                 pass       -> DMESG-WARN (ro-skl-i7-6700hq)
> Test kms_setmode:
>         Subgroup basic-clone-single-crtc:
>                 pass       -> DMESG-WARN (ro-skl-i7-6700hq)
> Test pm_rpm:
>         Subgroup basic-pci-d3-state:
>                 fail       -> DMESG-WARN (ro-skl-i7-6700hq)

All the remaining WARNs are the above "Potential atomic update failure"
 error message, so assuming the same bug as above.

> 
> ro-bdw-i5-
> 5250u  total:209  pass:172  dwarn:0   dfail:0   fail:0   skip:37 
> ro-bdw-i7-
> 5557U  total:209  pass:197  dwarn:0   dfail:0   fail:0   skip:12 
> ro-bdw-i7-
> 5600u  total:209  pass:180  dwarn:0   dfail:0   fail:1   skip:28 
> ro-byt-
> n2820     total:209  pass:169  dwarn:0   dfail:0   fail:3   skip:37 
> ro-hsw-i3-
> 4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
> ro-hsw-i7-
> 4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
> ro-ilk-i7-
> 620lm  total:209  pass:146  dwarn:0   dfail:0   fail:1   skip:62 
> ro-ilk1-i5-
> 650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
> ro-ivb-i7-
> 3770   total:209  pass:177  dwarn:0   dfail:0   fail:0   skip:32 
> ro-ivb2-i7-
> 3770  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
> ro-skl-i7-6700hq
> total:204  pass:175  dwarn:8   dfail:0   fail:0   skip:21 
> ro-snb-i7-
> 2620M  total:209  pass:170  dwarn:0   dfail:0   fail:1   skip:38 
> 
> Results at /archive/results/CI_IGT_test/RO_Patchwork_993/
> 
> 8621fb5 drm-intel-nightly: 2016y-05m-23d-18h-18m-33s UTC integration
> manifest
> a416d47 drm/i915/bxt: Sanitize CDCLK to fix breakage during S4 resume
> c1d96b1 drm/i915/gen9: Assume CDCLK PLL is off if it's not locked
> 
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Re: [PATCH v2 1/2] drm/i915/gen9: Assume CDCLK PLL is off if it's not locked

[Ville Syrjälä]

On Tue, May 24, 2016 at 03:38:32PM +0300, Imre Deak wrote:
> If the CDCLK PLL isn't locked or incorrectly configured we can just
> assume that it's off resulting in fully re-initializing both CDCLK PLL
> and CDCLK dividers. This way the CDCLK PLL sanitization added in the
> following patch can be done on BXT the same way as it's done on SKL.
> 
> v2: (Ville)
> - Remove the remaining PLL specific checks from skl_sanitize_cdclk() and
>   depend instead on the corresponding check in skl_dpll0_update().
> - Use vco == 0 instead of the corresponding boolean check in
>   skl_sanitize_cdclk().
> 
> CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 39 +++++++++++++++---------------------
>  1 file changed, 16 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c1e666b..47b2466 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5461,21 +5461,22 @@ skl_dpll0_update(struct drm_i915_private *dev_priv)
>  	u32 val;
>  
>  	dev_priv->cdclk_pll.ref = 24000;
> +	dev_priv->cdclk_pll.vco = 0;
>  
>  	val = I915_READ(LCPLL1_CTL);
> -	if ((val & LCPLL_PLL_ENABLE) == 0) {
> -		dev_priv->cdclk_pll.vco = 0;
> +	if ((val & LCPLL_PLL_ENABLE) == 0)
>  		return;
> -	}
>  
> -	WARN_ON((val & LCPLL_PLL_LOCK) == 0);
> +	if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
> +		return;
>  
>  	val = I915_READ(DPLL_CTRL1);
>  
> -	WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
> -			DPLL_CTRL1_SSC(SKL_DPLL0) |
> -			DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
> -		DPLL_CTRL1_OVERRIDE(SKL_DPLL0));
> +	if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
> +			    DPLL_CTRL1_SSC(SKL_DPLL0) |
> +			    DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
> +		    DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
> +		return;
>  
>  	switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
>  	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
> @@ -5490,7 +5491,6 @@ skl_dpll0_update(struct drm_i915_private *dev_priv)
>  		break;
>  	default:
>  		MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
> -		dev_priv->cdclk_pll.vco = 0;
>  		break;
>  	}
>  }
> @@ -5690,19 +5690,12 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  	if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
>  		goto sanitize;
>  
> +	intel_update_cdclk(dev_priv->dev);
>  	/* Is PLL enabled and locked ? */
> -	if ((I915_READ(LCPLL1_CTL) & (LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK)) !=
> -	    (LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK))
> +	if (dev_priv->cdclk_pll.vco == 0 ||
> +	    dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
>  		goto sanitize;
>  
> -	if ((I915_READ(DPLL_CTRL1) & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
> -				      DPLL_CTRL1_SSC(SKL_DPLL0) |
> -				      DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
> -	    DPLL_CTRL1_OVERRIDE(SKL_DPLL0))
> -		goto sanitize;
> -
> -	intel_update_cdclk(dev_priv->dev);
> -
>  	/* DPLL okay; verify the cdclock
>  	 *
>  	 * Noticed in some instances that the freq selection is correct but
> @@ -6608,14 +6601,14 @@ static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
>  	u32 val;
>  
>  	dev_priv->cdclk_pll.ref = 19200;
> +	dev_priv->cdclk_pll.vco = 0;
>  
>  	val = I915_READ(BXT_DE_PLL_ENABLE);
> -	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) {
> -		dev_priv->cdclk_pll.vco = 0;
> +	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
>  		return;
> -	}
>  
> -	WARN_ON((val & BXT_DE_PLL_LOCK) == 0);
> +	if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
> +		return;
>  
>  	val = I915_READ(BXT_DE_PLL_CTL);
>  	dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
> -- 
> 2.5.0

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH v2 2/2] drm/i915/bxt: Sanitize CDCLK to fix breakage during S4 resume

[Ville Syrjälä]

On Tue, May 24, 2016 at 03:38:33PM +0300, Imre Deak wrote:
> I noticed that during S4 resume BIOS incorrectly sets bits 18, 19 which
> are reserved/MBZ and sets the decimal frequency fields to all 0xff in
> the CDCLK register. The result is a hard lockup as display register
> accesses are attempted later. Work around this by sanitizing the CDCLK
> PLL/dividers the same way it's done on SKL.
> 
> While this is clearly a BIOS bug which should be fixed separately, it
> doesn't hurt to check/sanitize this regardless.
> 
> v2:
> - Use the same condition for VCO and CDCLK in broxton_init_cdclk as is
>   used in skl_init_cdclk for the same purpose.
> 
> CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 51 ++++++++++++++++++++++++++++++++++--
>  1 file changed, 49 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 47b2466..19f947f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5412,11 +5412,58 @@ static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
>  	intel_update_cdclk(dev_priv->dev);
>  }
>  
> +static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
> +{
> +	u32 cdctl, expected;
> +
> +	intel_update_cdclk(dev_priv->dev);
> +
> +	if (dev_priv->cdclk_pll.vco == 0 ||
> +	    dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
> +		goto sanitize;
> +
> +	/* DPLL okay; verify the cdclock
> +	 *
> +	 * Some BIOS versions leave an incorrect decimal frequency value and
> +	 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
> +	 * so sanitize this register.
> +	 */
> +	cdctl = I915_READ(CDCLK_CTL);
> +	/*
> +	 * Let's ignore the pipe field, since BIOS could have configured the
> +	 * dividers both synching to an active pipe, or asynchronously
> +	 * (PIPE_NONE).
> +	 */
> +	cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
> +
> +	expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
> +		   skl_cdclk_decimal(dev_priv->cdclk_freq);
> +	/*
> +	 * Disable SSA Precharge when CD clock frequency < 500 MHz,
> +	 * enable otherwise.
> +	 */
> +	if (dev_priv->cdclk_freq >= 500000)
> +		expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
> +
> +	if (cdctl == expected)
> +		/* All well; nothing to sanitize */
> +		return;
> +
> +sanitize:
> +	DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
> +
> +	/* force cdclk programming */
> +	dev_priv->cdclk_freq = 0;
> +
> +	/* force full PLL disable + enable */
> +	dev_priv->cdclk_pll.vco = -1;
> +}
> +
>  void broxton_init_cdclk(struct drm_i915_private *dev_priv)
>  {
> -	intel_update_cdclk(dev_priv->dev);
> +	bxt_sanitize_cdclk(dev_priv);
>  
> -	if (dev_priv->cdclk_pll.vco != 0)
> +	if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
>  		return;
>  
>  	/*
> -- 
> 2.5.0

-- 
Ville Syrjälä
Intel OTC
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Re: ✗ Ro.CI.BAT: failure for series starting with [v2,1/2] drm/i915/gen9: Assume CDCLK PLL is off if it's not locked

[Imre Deak]

On ti, 2016-05-24 at 16:18 +0300, Imre Deak wrote:
> On ti, 2016-05-24 at 13:02 +0000, Patchwork wrote:
> > == Series Details ==
> > 
> > Series: series starting with [v2,1/2] drm/i915/gen9: Assume CDCLK PLL
> > is off if it's not locked
> > URL   : https://patchwork.freedesktop.org/series/7631/
> > State : failure
> > 
> > == Summary ==
> > 
> > Series 7631v1 Series without cover letter
> > http://patchwork.freedesktop.org/api/1.0/series/7631/revisions/1/mbox
> > 
> > Test gem_busy:
> >         Subgroup basic-parallel-vebox:
> >                 dmesg-warn -> PASS       (ro-skl-i7-6700hq)
> > Test gem_exec_basic:
> >         Subgroup readonly-vebox:
> >                 pass       -> DMESG-WARN (ro-skl-i7-6700hq)
> 
> [drm:intel_pipe_update_start [i915]] *ERROR* Potential atomic update failure on pipe A
> 
> https://bugs.freedesktop.org/show_bug.cgi?id=95632
> 
> > Test gem_exec_flush:
> >         Subgroup basic-batch-kernel-default-cmd:
> >                 pass       -> FAIL       (ro-byt-n2820)
> 
> Stack trace:
>   #0 [__igt_fail_assert+0x101]
>   #1 [gem_execbuf+0x44]
>   #2 [batch+0x4bd]
>   #3 [__real_main481+0x308]
>   #4 [main+0x23]
>   #5 [__libc_start_main+0xf0]
>   #6 [_start+0x29]
>   #7 [+0x29]
> child 0 failed with exit status 99
> 
> (gem_exec_flush:6087) ioctl-wrappers-CRITICAL: Failed assertion: __gem_execbuf(fd, execbuf) == 0
> (gem_exec_flush:6087) ioctl-wrappers-CRITICAL: error: -22 != 0
> Subtest basic-batch-kernel-default-cmd failed.
> 
> https://bugs.freedesktop.org/show_bug.cgi?id=95372
> 
> > Test gem_exec_store:
> >         Subgroup basic-bsd:
> >                 pass       -> DMESG-WARN (ro-skl-i7-6700hq)
> > Test gem_ringfill:
> >         Subgroup basic-default-interruptible:
> >                 dmesg-warn -> PASS       (ro-skl-i7-6700hq)
> > Test gem_storedw_loop:
> >         Subgroup basic-default:
> >                 dmesg-warn -> PASS       (ro-skl-i7-6700hq)
> > Test kms_pipe_crc_basic:
> >         Subgroup bad-pipe:
> >                 dmesg-warn -> PASS       (ro-skl-i7-6700hq)
> > Test kms_psr_sink_crc:
> >         Subgroup psr_basic:
> >                 pass       -> DMESG-WARN (ro-skl-i7-6700hq)
> > Test kms_setmode:
> >         Subgroup basic-clone-single-crtc:
> >                 pass       -> DMESG-WARN (ro-skl-i7-6700hq)
> > Test pm_rpm:
> >         Subgroup basic-pci-d3-state:
> >                 fail       -> DMESG-WARN (ro-skl-i7-6700hq)
> 
> All the remaining WARNs are the above "Potential atomic update failure"
>  error message, so assuming the same bug as above.

I pushed the patchset to -dinq, thanks for the review.

> > ro-bdw-i5-
> > 5250u  total:209  pass:172  dwarn:0   dfail:0   fail:0   skip:37 
> > ro-bdw-i7-
> > 5557U  total:209  pass:197  dwarn:0   dfail:0   fail:0   skip:12 
> > ro-bdw-i7-
> > 5600u  total:209  pass:180  dwarn:0   dfail:0   fail:1   skip:28 
> > ro-byt-
> > n2820     total:209  pass:169  dwarn:0   dfail:0   fail:3   skip:37 
> > ro-hsw-i3-
> > 4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
> > ro-hsw-i7-
> > 4770r  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
> > ro-ilk-i7-
> > 620lm  total:209  pass:146  dwarn:0   dfail:0   fail:1   skip:62 
> > ro-ilk1-i5-
> > 650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
> > ro-ivb-i7-
> > 3770   total:209  pass:177  dwarn:0   dfail:0   fail:0   skip:32 
> > ro-ivb2-i7-
> > 3770  total:209  pass:181  dwarn:0   dfail:0   fail:0   skip:28 
> > ro-skl-i7-6700hq
> > total:204  pass:175  dwarn:8   dfail:0   fail:0   skip:21 
> > ro-snb-i7-
> > 2620M  total:209  pass:170  dwarn:0   dfail:0   fail:1   skip:38 
> > 
> > Results at /archive/results/CI_IGT_test/RO_Patchwork_993/
> > 
> > 8621fb5 drm-intel-nightly: 2016y-05m-23d-18h-18m-33s UTC integration
> > manifest
> > a416d47 drm/i915/bxt: Sanitize CDCLK to fix breakage during S4 resume
> > c1d96b1 drm/i915/gen9: Assume CDCLK PLL is off if it's not locked
> > 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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